View MB91F464HBPMC-GSE2_4711666.PDF datasheet online --- IC-ON-LINE

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MB91460H Series
2. Internal peripheral resources
* General-purpose ports : Maximum 108 ports * DMAC (DMA Controller) Maximum of 5 channels able to operate simultaneously 2 transfer sources (internal peripheral/software) Activation source can be selected using software Addressing mode specifies full 32-bit addresses (increment/decrement/fixed) Transfer mode (demand transfer/burst transfer/step transfer/block transfer) Transfer data size selectable from 8/16/32-bit Multi-byte transfer enabled (by software) DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H) * A/D converter (successive approximation type) 10-bit resolution: maximum 32 channels Conversion time: minimum 1 s * External interrupt inputs : maximum 16 channels 3 channels shared with CAN RX or I2C pins * Bit search module (for REALOS) Function to search the first bit position of `'1'', `'0'', `'changed'' from the MSB (most significant bit) within one word * LIN-USART (full duplex double buffer): 4 or 7 channels Clock synchronous/asynchronous selectable Sync-break detection Internal dedicated baud rate generator * I2C bus interface (supports 400 kbps): 2 channels Master/slave transmission and reception Arbitration function, clock synchronization function * CAN controller (C-CAN): 1 channel Maximum transfer speed: 1 Mbps 32 transmission/reception message buffers * Sound generator : 1 channel Tone frequency : PWM frequency divide-by-two (reload value + 1) * Alarm comparator : 1 channel Monitor external voltage Generate an interrupt in case of voltage lower/higher than the defined thresholds (reference voltage) * 16-bit PPG timer : maximum 16 channels * 16-bit reload timer: 8 channels * 16-bit free-run timer: 8 channels (1 channel each for ICU and OCU) * Input capture: maximum 8 channels (operates in conjunction with the free-run timer) * Output compare: maximum 8 channels (operates in conjunction with the free-run timer) * Up/Down counter: 2 channels (2*8-bit or 1*16-bit) * Watchdog timer * Real-time clock * Low-power consumption modes : Sleep/stop mode function * Low voltage detection circuit (Continued)
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(Continued) * Clock supervisor Monitors the sub-clock (32 kHz) and the main clock (4 MHz) , and switches to a recovery clock (CR oscillator, etc.) when the oscillations stop. * Clock modulator * Clock monitor * Sub-clock calibration Corrects the real-time clock timer when operating with the 32 kHz or CR oscillator * Main oscillator stabilization timer Generates an interrupt in sub-clock mode after the stabilization wait time has elapsed on the 23-bit stabilization wait time counter * Sub-oscillator stabilization timer Generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization wait time counter
3. Package and technology
* * * * Package : QFP-144 CMOS 180 nm technology Power supply range 3 V to 5 V (1.8 V internal logic provided by a step-down voltage converter) Operating temperature range: between - 40C and + 105C
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MB91460H Series
PRODUCT LINEUP
Feature
Max. core frequency (CLKB) Max. resource frequency (CLKP) Max. external bus frequency (CLKT) Max. CAN frequency (CLKCAN) Technology Watchdog Watchdog (RC osc. based) Bit Search Reset input (INITX)
MB91FV460B
100 MHz 50 MHz 50 MHz 50 MHz 0.18m yes yes (disengageable) yes yes
MB91F464HB
100 MHz 50 MHz 50 MHz 50 MHz 0.18m yes yes yes yes
Clock Modulator Clock Monitor Low Power Mode DMA MMU/MPU
yes yes yes 5 ch MPU (16 ch)*1
yes yes yes 5 ch MPU (8 ch)*1
Flash memory Flash Protection
Internal Flash memory 2112KB + external emulation SRAM with 64bit read data yes
416 KByte yes
D-RAM ID-RAM Flash-Cache (Instruction cache) Boot-ROM / BI-ROM
64 KByte 64 KByte 16 KByte 16 KByte Boot Flash + 1KB Boot ROM
24 KByte 16 KByte 8 KByte 4 KByte
RTC Free Running Timer ICU OCU Reload Timer PPG 16-bit
1 ch 12 ch 10 ch 8 ch 16 ch 32 ch
1 ch 8 ch*2 MD_3=0: 8 ch MD_3=1: 4 ch*3 MD_3=0: 8 ch MD_3=1: 4 ch*4 8 ch*5 MD_3=0: 16 ch MD_3=1: 8 ch*6
Sound Generator Up/Down Counter (8/16 bit)
1 ch (old) + 1 ch (new) 4 ch (8-bit) / 2 ch (16-bit)
1 ch (old) MD_3=0: 2 ch (8-bit) / 1 ch (16bit) MD_3=1: NA*7
C_CAN LIN-USART I2C (400K)
6 ch (128msg) 16 ch (FIFO) 8 ch
1 ch (32msg) MD_3=0: 3 ch + 4 ch FIFO*8 MD_3=1: 4 ch FIFO 2 ch
FR external bus
yes (32bit addr, 32bit data)
MD_3=0: no MD_3=1: yes (22bit addr, 16bit data)
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PIN ASSIGNMENT
MB91460H Series
1. MB91F464HB with MD_3=1
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VSS5 P07_6/A6 P07_7/A7 P06_0/A8 P06_1/A9 P06_2/A10 P06_3/A11 P06_4/A12 P06_5/A13 P06_6/A14 P06_7/A15 P05_0/A16 P05_1/A17 P05_2/A18 P05_3/A19 P05_4/A20 P05_5/A21 VDD35 VSS5 P01_0/D16 P01_1/D17 P01_2/D18 P01_3/D19 P01_4/D20 P01_5/D21 P01_6/D22 P01_7/D23 P00_0/D24 P00_1/D25 P00_2/D26 P00_3/D27 P00_4/D28 P00_5/D29 P00_6/D30 P00_7/D31 VDD35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
LQFP-144
(TOP VIEW)
VSS5 P10_0/SYSCLK P09_0/CSX0 P09_1/CSX1 P08_0/WRX0 P08_4/RDX P08_7/RDY P08_1/WRX1 P24_1/INT1 P23_0/RX0/INT8 P23_1/TX0 P23_2/INT9 P23_3 P23_4INT10 P23_5 P23_6/INT11 P23_7 VDD5 VSS5 P22_0/INT12 P22_1 P22_2/INT13 P22_3 P22_4/SDA0/INT14 P22_5/SCL0 P22_6/SDA1/INT15 P22_7/SCL1 P16_0/PPG8 P16_1/PPG9 P16_2/PPG10 P16_3/PPG11 P16_4/PPG12/SGA P16_5/PPG13/SGO P16_6/PPG14 P16_7/PPG15/ATGX VDD5 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
VDD35 P07_5/A5 P07_4/A4 P07_3/A3 P07_2/A2 P07_1/A1 P07_0/A0 P15_3/OCU3/TOT3 P15_2/OCU2/TOT2 P15_1/OCU1/TOT1 P15_0/OCU0/TOT0 P14_3/ICU3/TIN3/TTG3/11 P14_2/ICU2/TIN2/TTG2/10 P14_1/ICU1/TIN1/TTG1/9 P14_0/ICU0/TIN0/TTG0/8 P24_3/INT3 P24_2/INT2 VSS5 VDD5 P28_7/AN15 P28_6/AN14 P28_5/AN13 P28_4/AN12 P28_3/AN11 P28_2/AN10 P28_1/AN9 P28_0/AN8 P29_7/AN7 P29_6/AN6 P29_5/AN5 P29_4/AN4 P29_3/AN3 P29_2/AN2 P29_1/AN1 P29_0/AN0 VSS5
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD5 AVCC5 AVRH5 AVSS5 ALARM_0 P18_6/SCK7/CK7 P18_5/SOT7 P18_4/SIN7 P18_2/SCK6/CK6 P18_1/SOT6 P18_0/SIN6 P19_6/SCK5/CK5 P19_5/SOT5 P19_4/SIN5 P19_2/SCK4/CK4 P19_1/SOT4 P19_0/SIN4 VSS5 VDD5 VDD5R VDD5R VCC18C VSS5 NMIX INITX X1A X0A VSS5 X0 X1 MD_3 MONCLK MD_2 MD_1 MD_0 VSS5
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2. MB91F46HB with MD_3=0
VSS5 P27_6/AN22 P27_7/AN23 P26_0/AN24 P26_1/AN25 P26_2/AN26 P26_3/AN27 P26_4/AN28 P26_5/AN29 P26_6/AN30 P26_7/AN31 P24_4/INT4 P24_5/INT5 P24_6/INT6 P24_7/INT7 P21_0/SIN0 P21_1/SOT0 VDD35 VSS5 P14_4/ICU4/TIN4/TTG12/4 P14_5/ICU5/TIN5/TTG13/5 P14_6/ICU6/TIN6/TTG14/6 P14_7/ICU7/TIN7/TTG15/7 P15_4/OCU4/TOT4 P15_5/OCU5/TOT5 P15_6/OCU6/TOT6 P15_7/OCU7/TOT7 P17_0/PPG0 P17_1/PPG1 P17_2/PPG2 P17_3/PPG3 P17_4/PPG4 P17_5/PPG5 P17_6/PPG6 P17_7/PPG7 VDD35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
(TOP VIEW)
LQFP-144
VSS5 P20_0/SIN2/AIN0 P20_1/SOT2/BIN0 P20_2/SCK2/ZIN0/CK2 P20_4/SIN3/AIN1 P20_5/SOT3/BIN1 P20_6/SCK3/ZIN1/CK3 P24_0/INT0 P24_1/INT1 P23_0/RX0/INT8 P23_1/TX0 P23_2/INT9 P23_3 P23_4/INT10 P23_5 P23_6/INT11 P23_7 VDD5 VSS5 P22_0/INT12 P22_1 P22_2/INT13 P22_3 P22_4/SDA0/INT14 P22_5/SCL0 P22_6/SDA1/INT15 P22_7/SCL1 P16_0/PPG8 P16_1/PPG9 P16_2/PPG10 P16_3/PPG11 P16_4/PPG12/SGA P16_5/PPG13/SGO P16_6/PPG14 P16_7/PPG15/ATGX VDD5 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
VDD35 P27_5/AN21 P27_4/AN20 P27_3/AN19 P27_2/AN18 P27_1/AN17 P27_0/AN16 P15_3/OCU3/TOT3 P15_2/OCU2/TOT2 P15_1/OCU1/TOT1 P15_0/OCU0/TOT0 P14_3/ICU3/TIN3/TTG3/11 P14_2/ICU2/TIN2/TTG2/10 P14_1/ICU1/TIN1/TTG1/9 P14_0/ICU0/TIN0/TTG0/8 P24_3/INT3 P24_2/INT2 VSS5 VDD5 P28_7/AN15 P28_6/AN14 P28_5/AN13 P28_4/AN12 P28_3/AN11 P28_2/AN10 P28_1/AN9 P28_0/AN8 P29_7/AN7 P29_6/AN6 P29_5/AN5 P29_4/AN4 P29_3/AN3 P29_2/AN2 P29_1/AN1 P29_0/AN0 VSS5
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD5 AVCC5 AVRH5 AVSS5 ALARM_0 P18_6/SCK7/CK7 P18_5/SOT7 P18_4/SIN7 P18_2/SCK6/CK6 P18_1/SOT6 P18_0/SIN6 P19_6/SCK5/CK5 P19_5/SOT5 P19_4/SIN5 P19_2/SCK4/CK4 P19_1/SOT4 P19_0/SIN4 VSS5 VDD5 VDD5R VDD5R VCC18C VSS5 NMIX INITX X1A X0A VSS5 X0 X1 MD_3 MONCLK MD_2 MD_1 MD_0 VSS5
MB91460H Series
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MB91460H Series
PIN DESCRIPTION
1. MB91F464HB with MD_3=1
Pin no. 2, 3 4 to 11 12 to 17 20 to 27 28 to 35 38 39 40 41 42 43 Pin name P07_6, P07_7 A6, A7 P06_0 to P06_7 A8 to A15 P05_0 to P05_5 A16 to A21 P01_0 to P01_7 D16 to D23 P00_0 to P00_7 D24 to D31 P10_0 SYSCLK P09_0 CSX0 P09_1 CSX1 P08_0 WRX0 P08_4 RDX P08_7 RDY P08_1 44 WRX1 INT0 45 P24_1 INT1 P23_0 46 RX0 INT8 47 P23_1 TX0 I/O A I/O A I/O A I/O A I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O circuit type* B B A A A A A A A A A Function General-purpose input/output port Signal pins of external address bus (bit6 to bit7) General-purpose input/output port Signal pins of external address bus (bit8 to bit15) General-purpose input/output port Signal pins of external address bus (bit16 to bit21) General-purpose input/output port Signal pins of external data bus (bit16 to bit23) General-purpose input/output port Signal pins of external data bus (bit24 to bit31) General-purpose input/output port External bus clock output pin General-purpose input/output port Chip select output pins General-purpose input/output port Chip select output pins General-purpose input/output port External write strobe output pins General-purpose input/output port External read strobe output pin General-purpose input/output port External ready input pin General-purpose input/output port External write strobe output pins External interrupt input, can only be used in general-purpose IO port mode General-purpose input/output port External interrupt input pins General-purpose input/output port RX input pin of CAN0 External interrupt input pins General-purpose input/output port TX output pin of CAN0
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Pin no. Pin name P16_5 69 PPG13 SGO 70 P16_6 PPG14 P16_7 71 74 to 76 77 78 79 80 82 83 84 85 92 93 PPG15 ATGX MD_0 to MD_2 MONCLK MD_3 X1 X0 X0A X1A INITX NMIX P19_0 SIN4 P19_1 SOT4 P19_2 94 SCK4 CK4 95 96 P19_4 SIN5 P19_5 SOT5 P19_6 97 SCK5 CK5 98 99 P18_0 SIN6 P18_1 SOT6 I/O I/O A A I/O A I/O I/O A A I/O A I O I -- -- -- -- I I I/O I/O G M H J1 J1 J2 J2 H H A A I/O A I/O A I/O A I/O I/O circuit type* Function General-purpose input/output port Output pins of PPG timer SGO output pin of sound generator General-purpose input/output port Output pins of PPG timer General-purpose input/output port Output pins of PPG timer A/D converter external trigger input pin Mode setting pins Clock monitor pin Mode setting pin Clock (oscillation) output Clock (oscillation) input Sub clock (oscillation) input Sub clock (oscillation) output External reset input pin Non-maskable interrupt input pin General-purpose input/output port Data input pin of USART4 General-purpose input/output port Data output pin of USART4 General-purpose input/output port Clock input/output pin of USART4 External clock input pin of free-run timer 4 General-purpose input/output port Data input pin of USART5 General-purpose input/output port Data output pin of USART5 General-purpose input/output port Clock input/output pin of USART5 External clock input pin of free-run timer 5 General-purpose input/output port Data input pin of USART6 General-purpose input/output port Data output pin of USART6
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[Power supply/Ground pins] Pin no. Pin name 1, 19, 37, 55, 73, 81, 86, 91, 109, 127 54, 72, 90, 108, 126 88, 89 105 107 106 87 18, 36, 144 VSS5 VDD5 VDD5R AVSS5 AVCC5 AVRH5 VCC18C VDD35 Supply
I/O Ground pins Power supply pins
Function
Power supply pins for internal regulator Analog ground pin for A/D converter Power supply pin for A/D converter Reference power supply pin for A/D converter Capacitor connection pin for internal regulator Power supply pins for external bus part of I/O ring
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2. MB91F464HB with MD_3=0
Pin no. 2 to 3 4 to 11 12 to 15 16 17 Pin name P27_6 to P27_7 AN22 to AN23 P26_0 to P26_7 AN24 to AN31 P24_4 to P24_7 INT4 to INT7 P21_0 SIN0 P21_1 SOT0 P14_4 to P14_7 20 to 23 ICU4 to ICU7 TIN4 to TIN7 TTG4/12 to TTG7/15 P15_4 to P15_7 24 to 27 OCU4 to OCU7 TOT4 to TOT7 28 to 35 P17_0 to P17_7 PPG0 to PPG7 P20_0 38 SIN2 AIN0 P20_1 39 SOT2 BIN0 P20_2 40 SCK2 ZIN0 CK2 P20_4 41 SIN3 AIN1 P20_5 42 SOT3 BIN1 I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O I/O I/O I/O I/O I/O I/O circuit type* B B A A A Function General-purpose input/output ports Analog input pins of A/D converter General-purpose input/output ports Analog input pins of A/D converter General-purpose input/output ports External interrupt input pins General-purpose input/output ports Data input pin of USART0 General-purpose input/output ports Data output pin of USART0 General-purpose input/output ports Input capture input pins External trigger input pins of reload timer External trigger input pins of PPG timer General-purpose input/output ports Output compare output pins Reload timer output pins General-purpose input/output ports Output pins of PPG timer General-purpose input/output ports Data input pin of USART2 Up/down counter input pin General-purpose input/output ports Data output pin of USART2 Up/down counter input pin General-purpose input/output ports Clock input/output pin of USART2 Up/down counter input pin External clock input pin of free-run timer 2 General-purpose input/output ports Data input pin of USART3 Up/down counter input pin General-purpose input/output ports Data output pin of USART3 Up/down counter input pin
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MB91460H Series
Pin no. 63 64 to 67 Pin name P22_7 SCL1 P16_0 to P16_3 PPG8 to PPG11 P16_4 68 PPG12 SGA P16_5 69 PPG13 SGO 70 P16_6 PPG14 P16_7 71 74 to 76 77 78 79 80 82 83 84 85 92 93 PPG15 ATGX MD_0 to MD_2 MONCLK MD_3 X1 X0 X0A X1A INITX NMIX P19_0 SIN4 P19_1 SOT4 P19_2 94 SCK4 CK4 95 96 P19_4 SIN5 P19_5 SOT5 I/O I/O A A I/O A I O I -- -- -- -- I I I/O I/O G M H J1 J1 J2 J2 H H A A I/O A I/O A I/O A I/O A I/O I/O I/O I/O circuit type* C A Function General-purpose input/output ports I2C bus clock input/output pin (open drain) General-purpose input/output ports Output pins of PPG timer General-purpose input/output ports Output pins of PPG timer SGA output pin of sound generator General-purpose input/output ports Output pins of PPG timer SGO output pin of sound generator General-purpose input/output ports Output pins of PPG timer General-purpose input/output ports Output pins of PPG timer A/D converter external trigger input pin Mode setting pins Clock monitor pin Mode setting pins Clock (oscillation) output Clock (oscillation) input Sub clock (oscillation) input Sub clock (oscillation) output External reset input pin Non-maskable interrupt input pin General-purpose input/output ports Data input pin of USART4 General-purpose input/output ports Data output pin of USART4 General-purpose input/output ports Clock input/output pin of USART4 External clock input pin of free-run timer 4 General-purpose input/output ports Data input pin of USART5 General-purpose input/output ports Data output pin of USART5
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MB91460H Series
Pin no. Pin name P19_6 97 SCK5 CK5 98 99 P18_0 SIN6 P18_1 SOT6 P18_2 100 SCK6 CK6 101 102 P18_4 SIN7 P18_5 SOT7 P18_6 103 104 110 to 117 118 to 125 128 129 SCK7 CK7 ALARM_0 P29_0 to P29_7 AN0 to AN7 P28_0 to P28_7 AN8 to AN15 P24_2 INT2 P24_3 INT3 P14_0 to P14_3 130 to 133 ICU0 to ICU3 TIN0 to TIN3 TTG0/8 to TTG3/11 P15_0 to P15_3 134 to 137 OCU0 to OCU3 TOT0 to TOT3 138 to 143 P27_0 to P27_5 AN16 to AN21 I/O B I/O A I/O A I I/O I/O I/O I/O N B B A A I/O A I/O I/O A A I/O A I/O I/O A A I/O A I/O I/O circuit type* Function General-purpose input/output ports Clock input/output pin of USART5 External clock input pin of free-run timer 5 General-purpose input/output ports Data input pin of USART6 General-purpose input/output ports Data output pin of USART6 General-purpose input/output ports Clock input/output pin of USART6 External clock input pin of free-run timer 6 General-purpose input/output ports Data input pin of USART7 General-purpose input/output ports Data output pin of USART7 General-purpose input/output ports Clock input/output pin of USART7 External clock input pin of free-run timer 7 Alarm comparator input pin General-purpose input/output ports Analog input pins of A/D converter General-purpose input/output ports Analog input pins of A/D converter General-purpose input/output ports External interrupt input pin General-purpose input/output ports External interrupt input pin General-purpose input/output ports Input capture input pins External trigger input pins of reload timer External trigger input pins of PPG timer General-purpose input/output ports Output compare output pins Reload timer output pins General-purpose input/output ports Analog input pins of A/D converter
* : For information about the I/O circuit type, refer to " I/O CIRCUIT TYPES". 16 DS07-16616-1E
MB91460H Series
[Power supply/Ground pins] Pin no. Pin name 1, 19, 37, 55, 73, 81, 86, 91, 109, 127 54, 72, 90, 108, 126 88, 89 105 107 106 87 18, 36, 144 VSS5 VDD5 VDD5R AVSS5 AVCC5 AVRH5 VCC18C VDD35 Supply
I/O Ground pins Power supply pins
Function
Power supply pins for internal regulator Analog ground pin for A/D converter Power supply pin for A/D converter Reference power supply pin for A/D converter Capacitor connection pin for internal regulator Power supply pins for external bus part of I/O ring
* : For information about the I/O circuit type, refer to " I/O CIRCUIT TYPES".
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MB91460H Series
I/O CIRCUIT TYPES
Type A Circuit
pull-up control driver strength control data line
Remarks CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50k approx.
pull- down control R CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input standby control for input shutdown
B
pull-up control driver strength control data line
CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50k approx. Analog input
pull- down control R CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input standby control for input shutdown analog input
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Type K Circuit
pull-up control driver strength control data line
Remarks CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50k approx. LCD SEG/COM output
pull- down control R CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input standby control for input shutdown LCD SEG/COM
L
pull-up control driver strength control data line
pull- down control R CMOS hysteresis type1
CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function) TTL input with input shutdown function Programmable pull-up resistor: 50k approx. Analog input LCD Voltage input
CMOS hysteresis type2
Automotive inputs
TTL input standby control for input shutdown VLCD
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Type M
tri-state control data line
Circuit
Remarks CMOS level tri-state output (IOL = 5mA, IOH = -5mA)
N Analog input pin with protection
analog input line
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MB91460H Series
HANDLING DEVICES
1. Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage higher than (VDD5, VDD35 or HVDD5 *1) or less than (VSS5 or HVSS5 *1) is applied to an input or output pin or if a voltage exceeding the rating is applied between the power supply pins and ground pins. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore, be very careful not to apply voltages in excess of the absolute maximum ratings. Note *1: HVDD5, HVSS5 are available only on devices having Stepper Motor Controller.
2. Handling of unused input pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down resistor (2K to 10K) or enable internal pullup or pulldown resisters (PPER/PPCR) before the input enable (PORTEN) is activated by software. The mode pins MD_x can be connected to VSS5 or VDD5 directly. Unused ALARM input pins can be connected to AVSS5 directly.
3. Power supply pins
In MB91460 series, devices including multiple power supply pins and ground pins are designed as follows; pins necessary to be at the same potential are interconnected internally to prevent malfunctions such as latch-up. All of the power supply pins and ground pins must be externally connected to the power supply and ground respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground level rising and to follow the total output current ratings. Furthermore, the power supply pins and ground pins of the MB91460 series must be connected to the current supply source via a low impedance. It is also recommended to connect a ceramic capacitor of approximately 0.1 F as a bypass capacitor between power supply pin and ground pin near this device. This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 F (use a X7R ceramic capacitor) to VCC18C pin for the regulator.
4. Crystal oscillator circuit
Noise in proximity to the X0 (X0A) and X1 (X1A) pins can cause the device to operate abnormally. Printed circuit boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass capacitors connected to ground, are located near the device and ground. It is recommended that the printed circuit board layout be designed such that the X0 and X1 pins or X0A and X1A pins are surrounded by ground plane for the stable operation. Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this device.
5. Notes on using external clock
When using the external clock, it is necessary to simultaneously supply the X0 (X0A) and the X1 (X1A) pins. In the described combination, X1 (X1A) should be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. At X0 and X1, a frequency up to 16 MHz is possible. (Continued)
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(Continued) Example of using opposite phase supply
X0 (X0A) X1 (X1A)
6. Mode pins (MD_x)
These pins should be connected directly to the power supply or ground pins. To prevent the device from entering test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and power supply pin or ground pin on the printed circuit board as possible and connect them with low impedance.
7. Notes on operating in PLL clock mode
If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may continue to operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this selfrunning operation cannot be guaranteed.
8. Pull-up control
The AC standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin.
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2. MB91F464HB with MD_3=0
FR60 CPU core D-RAM 16Kbytes Bit search Flash memory
416 Kbytes (MB91F464HB) D-bus 32
Flash-Cache 8 Kbytes
I-bus 32
CAN 1 channel 32 <-> 16 bus adapter
RX0 TX0
ID-RAM
16 Kbytes
Bus converter
DMAC 5 channels Clock supervisor Clock control
TTG0/8 to TTG7/15 PPG0 to PPG15 TIN0 to TIN7 TOT0 to TOT7 CK2 to CK7
R-bus 16
Clock modulator Clock monitor Interrupt controller External interrupt 16 channels
INT0 to INT15 MONCLK
PPG timer 16 channels Reload timer 8 channels Free-run timer 8 channels Input capture 8 channels Output compare 8 channels Up/down counter 2 channels
LIN-USART 7 channels I2C 2 channels Real time clock
SIN2 to SIN7,SIN0 SOT2 to SOT7,SOT0 SCK2 to SCK7 SDA0 to SDA1 SCL0 to SCL1
ICU0 to ICU7
OCU0 to OCU7 AIN0 to AIN1 BIN0 to BIN1 ZIN0 to ZIN1
A/D converter 32 channels
AN0 to AN31 ATGX
ALARM_0
Alarm comparator 1 channel
Sound generator 1 channel
SGA SGO
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CPU AND CONTROL UNIT
The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced instructions for embedded applications.
1. Features
* Adoption of RISC architecture Basic instruction: 1 instruction per cycle * General-purpose registers: 32-bit x 16 registers * 4 Gbytes linear memory space * Multiplier installed 32-bit x 32-bit multiplication: 5 cycles 16-bit x 16-bit multiplication: 3 cycles * Enhanced interrupt processing function Quick response speed (6 cycles) Multiple-interrupt support Level mask function (16 levels) * Enhanced instructions for I/O operation Memory-to-memory transfer instruction Bit processing instruction Basic instruction word length: 16 bits * Low-power consumption Sleep mode/stop mode
2. Internal architecture
* The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent of each other. * A 32-bit 16-bit buffer is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and peripheral resources. * A Harvard Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between the CPU and the bus controller.
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3. Programming model 3.1. Basic programming model
32 bits Initial value
R0 R1 ... ... ... ... XXXX XXXXH ... ... ... ... AC FP SP ... XXXX XXXXH 0000 0000H
General-purpose registers
R12 R13 R14 R15
Program counter Program status Table base register Return pointer System stack pointer User stack pointer Multiply & divide registers
PC PS TBR RP SSP USP MDH MDL ILM SCR CCR
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4. Registers 4.1. General-purpose register
32 bits Initial value
R0 R1 ... ... R12 R13 R14 R15 AC FP SP ... ... XXXX XXXXH ... ... ... ... ... XXXX XXXXH 0000 0000H
Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation operations and as pointers for memory access. Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular applications. R13 : Virtual accumulator R14 : Frame pointer R15 : Stack pointer Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value).
4.2.
PS (Program Status)
This register holds the program status, and is divided into three parts, ILM, SCR, and CCR. All undefined bits (-) in the diagram are reserved bits. The read values are always "0". Write access to these bits is invalid. Bit position bit 31
bit 20 bit 16 bit 10 bit 8 bit 7 bit 0
ILM
SCR
CCR
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MB91460H Series
4.3. CCR (Condition Code Register)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Initial value
- 000XXXXB
SV
S
I
N
Z
V
C
SV : Supervisor flag S I Z V : Stack flag : Interrupt enable flag : Zero flag : Overflow flag
N : Negative enable flag
C : Carry flag
4.4.
SCR (System Condition Register)
bit 10 bit 9 bit 8
Initial value
XX0B
D1
D0
T
Flag for step division (D1, D0) This flag stores interim data during execution of step division. Step trace trap flag (T) This flag indicates whether the step trace trap is enabled or disabled. The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution of user programs.
4.5.
ILM (Interrupt Level Mask register)
bit 20 bit 19 bit 18 bit 17 bit 16
Initial value
01111B
ILM4 ILM3 ILM2 ILM1 ILM0
This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking. The register is initialized to value "01111B" at reset.
4.6.
PC (Program Counter)
bit 31 bit 0
Initial value
XXXXXXXXH
The program counter indicates the address of the instruction that is being executed. The initial value at reset is undefined. 32 DS07-16616-1E
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4.7. TBR (Table Base Register)
bit 31 bit 0
Initial value
000FFC00H
The table base register stores the starting address of the vector table used in EIT processing. The initial value at reset is 000FFC00H.
4.8.
RP (Return Pointer)
bit 31 bit 0
Initial value
XXXXXXXXH
The return pointer stores the address for return from subroutines. During execution of a CALL instruction, the PC value is transferred to this RP register. During execution of a RET instruction, the contents of the RP register are transferred to PC. The initial value at reset is undefined.
4.9.
USP (User Stack Pointer)
bit 31 bit 0
Initial value
XXXXXXXXH
The user stack pointer, when the S flag is "1", this register functions as the R15 register. * The USP register can also be explicitly specified. The initial value at reset is undefined. * This register cannot be used with RETI instructions.
4.10. Multiply & divide registers
bit 31 MDH MDL bit 0
These registers are for multiplication and division, and are each 32 bits in length. The initial value at reset is undefined.
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MB91460H Series
3.2. Flash access timing settings in CPU mode
The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or maximum clock modulation) for Flash read and write access.
3.2.1.
Flash read timing settings (synchronous read)
ATD 0 0 1 1 ALEH 0 0 1 1 EQ 0 1 3 3 WEXH WTC 1 2 4 4 Remark to 24 MHz to 48 MHz to 96 MHz to 100 MHz
Core clock (CLKB)
3.2.2.
Flash write timing settings (synchronous write)
ATD 0 0 0 1 1 1 ALEH EQ WEXH 0 0 0 0 0 0 WTC 3 4 5 6 7 7 Remark to 16 MHz to 32 MHz to 48 MHz to 64 MHz to 96 MHz to 100 MHz
Core clock (CLKB)
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3.3. Address mapping from CPU to parallel programming mode
The following tables show the calculation from CPU addresses to flash macro addresses which are used in parallel programming.
3.3.1.
Address mapping MB91F464HB
Flash sectors SA4, SA6 (8 Kbyte) SA5, SA7 (8 Kbyte) SA14, SA16, SA18 (64 Kbyte) SA15, SA17, SA19 (64 Kbyte) FA (flash address) Calculation FA := addr - addr%00:4000h + (addr%00:4000h)/2 (addr/2)%4 + addr%4 - 0D:0000h FA := addr - addr%00:4000h + (addr%00:4000h)/2 + 00:2000h - (addr/2)%4 + addr%4 - 0D:0000h FA := addr - addr%02:0000 + (addr%02:0000h)/2 (addr/2)%4 + addr%4 FA := addr - addr%02:0000h + (addr%02:0000h)/2 + 01:0000h - (addr/2)%4 + addr%4
CPU Address Condition (addr) 14:8000h to 14:FFFFh 14:8000h to 14:FFFFh 0A:0000h to 0F:FFFFh 0A:0000h to 0F:FFFFh addr[2]==0
addr[2]==1
addr[2]==0
addr[2]==1
Note: FA result is without 20:0000h offset for parallel Flash programming. Set offset by keeping FA[21] = 1 as described in section "Parallel Flash programming mode".
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MB91460H Series
4. Parallel Flash programming mode 4.1. Flash configuration in parallel Flash programming mode
Parallel Flash programming mode (MD[2:0] = 111): MB91F464HB
FA[20:0]
001F:FFFFh 001F:0000h 001E:FFFFh 001E:0000h 001D:FFFFh 001D:0000h 001C:FFFFh 001C:0000h 001B:FFFFh 001B:0000h 001A:FFFFh 001A:0000h SA19 (64KB)
SA18 (64KB)
SA17 (64KB)
SA16 (64KB)
SA15 (64KB)
SA14 (64KB)
SA13 (64KB)
SA12 (64KB)
SA11 (64KB)
SA10 (64KB)
SA9 (64KB)
SA8 (64KB) 0017:FFFFh 0017:E000h 0017:DFFFh 0017:C000h 0017:BFFFh 0017:A000h 0017:9FFFh 0017:8000h
SA7 (8KB)
SA6 (8KB)
SA5 (8KB)
SA4 (8KB)
SA3 (8KB)
SA2 (8KB)
SA1 (8KB)
SA0 (8KB) FA[1:0]=00 16bit write mode DQ[15:0] FA[1:0]=10 DQ[15:0]
Remark: Always keep FA[0] = 0 and FA[20] = 1 Legend Memory available in this area Memory not available in this area
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4.2. Pin connections in parallel programming mode
Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory's interface circuit enables direct control of the Flash memory unit from external pins by directly linking some of the signals to GP-Ports. Please see table below for signal mapping. In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set when writing/erasing using the parallel Flash programmer. In this mode, all operations of the 8.5 Mbits Flash memory's Auto Algorithms are available. Correspondence between MBM29LV400TC and Flash Memory Control Signals MBM29LV400TC MB91F464HB FR-CPU mode External pins external pins Flash memory mode RESET RY/BY BYTE WE OE CE A-1 A0 to A3 A4 to A7 Internal address bus A8 to A11 A12 to A15 A16 to A18 A19 DQ0 to DQ7 DQ8 to DQ15 Internal data bus FA9 to FA12 FA13 to FA16 FA17 to FA19 FA20 DQ0 to DQ7 DQ8 to DQ15 Internal control signal + control via interface circuit INITX FMCS:RDY bit Internally fixed to `H' FRSTX MD2 MD1 MD0 RY/BYX BYTEX WEX OEX CEX ATDIN EQIN TESTX RDYI FA0 FA1 to FA4 FA5 to FA8 Normal function INITX GP16_6 MD2 MD1 MD0 GP18_2 GP16_4 GP16_7 GP07_7 GP07_6 GP18_6 GP18_5 GP16_5 GP18_4 GP05_5 GP19_0 to GP19_2, GP19_4 GP19_5 to GP19_6, GP18_0 to GP18_1 GP06_0 to GP06_3 GP06_4 to GP06_7 GP05_0 to GP05_2 GP05_3 GP00_0 to GP00_7 GP01_0 to GP01_7 Pin number 84 70 76 75 74 100 68 71 3 2 103 102 69 101 17 92 to 95 96 to 99 4 to 7 8 to 11 12 to 14 15 28 to 35 20 to 27 Set to `1' Set to `0' Set to `0' Set to `1' Set to `0' Set to `0' Set to `1' Set to `1' Set to `1'
Comment
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5. Poweron Sequence in parallel programming mode
The flash memory can be accessed in programming mode after a certain wait time, which is needed for Security Vector fetch: * Minimum wait time after VDD5/VDD5R power on: * Minimum wait time after INITX rising: 2.76 ms 1.0 ms
6. Flash Security 6.1. Vector addresses
Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1, BSV2) controlling the protection functions of the Flash Security Module: FSV1: 0x14:8000 FSV2: 0x14:8008 BSV1: 0x14:8004 BSV2: 0x14:800C
6.2.
Security Vector FSV1
The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes and the individual write protection of the 8 KBytes sectors.
6.2.1.
FSV1 (bit31 to bit16)
The setting of the Flash Security Vector FSV1 bits [31:16] is responsible for the read and write protection modes. Explanation of the bits in the Flash Security Vector FSV1[31:16] FSV1[18] FSV1[17] FSV1[16] FSV1[31:19] Write Protection Write Protection Read Protection Level set all to `0' set all to `0' set to `0' set to `0' set to `0' set to `1' set to `1' set to `0'
Flash Security Mode Read Protection (all device modes, except INTVEC mode MD[2:0]="000") Write Protection (all device modes, without exception) Read Protection (all device modes, except INTVEC mode MD[2:0]="000") and Write Protection (all device modes) Read Protection (all device modes, except INTVEC mode MD[2:0]="000") Write Protection (all device modes, except INTVEC mode MD[2:0]="000") Read Protection (all device modes, except INTVEC mode MD[2:0]="000") and Write Protection (all device modes except INTVEC mode MD[2:0]="000")
set all to `0'
set to `0'
set to `1'
set to `1'
set all to `0' set all to `0'
set to `1' set to `1'
set to `0' set to `1'
set to `1' set to `0'
set all to `0'
set to `1'
set to `1'
set to `1'
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6.2.2. FSV1 (bit15 to bit0) MB91F464HB
The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write protection of the 8 KBytes sectors. It is only evaluated if write protection bit FSV1[17] is set. Explanation of the bits in the Flash Security Vector FSV1[15:0] Enable Write Disable Write FSV1 bit Sector Protection Protection FSV1[3:0] FSV1[4] FSV1[5] FSV1[6] FSV1[7] FSV1[15:8] SA4 SA5 SA6 SA7 set to "0" set to "0" set to "0" set to "0" -- set to "1" set to "1" set to "1" not available
Comment not available Write protection is mandatory!
Note: It is mandatory to always set the sector where the Flash Security Vectors FSV1 and FSV2 are located to write protected (here sector SA4). Otherwise it is possible to overwrite the Security Vector to a setting where it is possible to either read out the Flash content or manipulate data by writing. See section "Flash access in CPU mode" for an overview about the sector organisation of the Flash Memory.
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6.3. Security Vector FSV2 MB91F464HB
The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write protection of the 64 KByte sectors. It is only evaluated if write protection bit FSV1[17] is set. Explanation of the bits in the Flash Security Vector FSV2[31:0] FSV2 bit FSV2[5:0] FSV2[6] FSV2[7] FSV2[8] FSV2[9] FSV2[10] FSV2[11] FSV2[31:12] Sector SA14 SA15 SA16 SA17 SA18 SA19 Enable Write Disable Write Protection Protection set to "0" set to "0" set to "0" set to "0" set to "0" set to "0" set to "1" set to "1" set to "1" set to "1" set to "1" set to "1" not available Comment not available
Note : See section "Flash access in CPU mode" for an overview about the sector organisation of the Flash Memory.
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MEMORY SPACE
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access. * Direct addressing area The following address space area is used for I/O. This area is called direct addressing area, and the address of an operand can be specified directly in an instruction. The size of directly addressable area depends on the length of the data being accessed as shown below. Byte data access : 000H to 0FFH Half word access : 000H to 1FFH Word data access : 000H to 3FFH
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MEMORY MAPS
1. MB91F464HB
MB91F464HB
00000000H 00000400H 00001000H 00002000H 00004000H 00006000H 00007000H 00008000H
I/O (direct addressing area) I/O DMA
Flash-Cache (8 Kbytes)
Flash memory control
0000B000H 0000C000H 0000D000H
Boot ROM (4 Kbytes) CAN
0002C000H 00030000H 00034000H 00040000H 00080000H 000A0000H
D-RAM (0 wait, 16 Kbytes) ID-RAM (16 Kbytes)
External bus area
Flash memory (384 Kbytes) 00100000H 00148000H 00150000H 00180000H External bus area 00500000H External data bus FFFFFFFFH
External bus area Flash memory (32 Kbytes)
Note:
Access prohibited areas
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I/O MAP
1. MB91F464HB
Address 000000H Register +0 PDR0 [R/W] XXXXXXXX +1 PDR1 [R/W] XXXXXXXX +2 PDR2 [R/W] XXXXXXXX +3 PDR3 [R/W] XXXXXXXX Block T-unit port data register
Read/write attribute Register initial value after reset Register name (column 1 register at address 4n, column 2 register at address 4n + 1...) Leftmost register address (for word access, the register in column 1 becomes the MSB side of the data.) Note : Initial values of register bits are represented as follows: " 1 " : Initial value " 1 " " 0 " : Initial value " 0 " " X " : Initial value " undefined " " - " : No physical register at this location Access is barred with an undefined data access attribute.
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MB91460H Series
Address +0 000000H 000004H 000008H 00000CH 000010H 000014H 000018H 00001CH 000020H to 00002CH 000030H 000034H 000038H 00003CH 000040H SCR00 [R/W,W] 00000000 ESCR00 [R/W] 00000X00 EIRR0 [R/W] XXXXXXXX EIRR1 [R/W] XXXXXXXX DICR [R/W] -------0 PDR00 [R/W] XXXXXXXX Reserved PDR08 [R/W] X--X---X Reserved PDR16 [R/W] XXXXXXXX PDR20 [R/W] - XXX - XXX PDR24 [R/W] XXXXXXXX PDR28 [R/W] XXXXXXXX +1
Register +2 Reserved PDR06 [R/W] XXXXXXXX PDR10 [R/W] -------X PDR14 [R/W] XXXXXXXX PDR18 [R/W] - XXX - XXX PDR22 [R/W] XXXXXXXX PDR26 [R/W] XXXXXXXX Reserved +3 Reserved PDR07 [R/W] XXXXXXXX Reserved PDR15 [R/W] XXXXXXXX PDR19 [R/W] - XXX - XXX PDR23 [R/W] XXXXXXXX PDR27 [R/W] XXXXXXXX Reserved PDR01 [R/W] XXXXXXXX PDR05 [R/W] - - XXXXXX PDR09 [R/W] - - - - - - XX Reserved PDR17 [R/W] XXXXXXXX PDR21 [R/W] - - - - - - XX Reserved PDR29 [R/W] XXXXXXXX Reserved ENIR0 [R/W] 00000000 ENIR1 [R/W] 00000000 HRCL [R/W] 0 - - 11111 Reserved SMR00 [R/W,W] 00000000 ECCR00 [R/W,R,W] -00000XX Reserved SCR02 [R/W,W] 00000000 ESCR02 [R/W] 00000X00 SMR02 [R/W,W] 00000000 ECCR02 [R/W,R,W] -00000XX SSR02 [R/W,R] 00001000 RDR02/TDR02 [R/W] 00000000 SSR00 [R/W,R] 00001000 RDR00/TDR00 [R/W] 00000000 ELVR0 [R/W] 00000000 00000000 ELVR1 [R/W] 00000000 00000000 RBSYNC
Block
R-bus Port Data Register
External interrupt (INT 0 to INT 7) External interrupt (INT 8 to INT 15) Delay interrupt Reserved
LIN-USART 0
000044H 000048H 00004CH 000050H
Reserved
Reserved
LIN-USART 2
000054H
Reserved
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Address +0 000058H SCR03 [R/W,W] 00000000 ESCR03 [R/W] 00000X00 SCR04 [R/W,W] 00000000 ESCR04 [R/W] 00000X00 SCR05 [R/W,W] 00000000 ESCR05 [R/W] 00000X00 SCR06 [R/W,W] 00000000 ESCR06 [R/W] 00000X00 SCR07 [R/W,W] 00000000 ESCR07 [R/W] 00000X00 BGR100 [R/W] 00000000 BGR102 [R/W] 00000000 BGR104 [R/W] 00000000 BGR106 [R/W] 00000000 +1 SMR03 [R/W,W] 00000000 ECCR03 [R/W,R,W] -00000XX SMR04 [R/W,W] 00000000 ECCR04 [R/W,R,W] -00000XX SMR05 [R/W,W] 00000000 ECCR05 [R/W,R,W] -00000XX SMR06 [R/W,W] 00000000 ECCR06 [R/W,R,W] -00000XX SMR07 [R/W,W] 00000000 ECCR07 [R/W,R,W] -00000XX BGR000 [R/W] 00000000 BGR002 [R/W] 00000000 BGR004 [R/W] 00000000 BGR006 [R/W] 00000000 Register +2 SSR03 [R/W,R] 00001000 +3 RDR03/TDR03 [R/W] 00000000 Block
LIN-USART 3
00005CH
Reserved RDR04/TDR04 [R/W] 00000000 FCR04 [R/W] 0001 - 000 RDR05/TDR05 [R/W] 00000000 FCR05 [R/W] 0001 - 000 RDR06/TDR06 [R/W] 00000000 FCR06 [R/W] 0001 - 000 RDR07/TDR07 [R/W] 00000000 FCR07 [R/W] 0001 - 000 Reserved BGR003 [R/W] 00000000 BGR005 [R/W] 00000000 BGR007 [R/W] 00000000 Reserved Baud rate Generator LIN-USART 0 to 7
000060H
SSR04 [R/W,R] 00001000 FSR04 [R] - - - 00000 SSR05 [R/W,R] 00001000 FSR05 [R] - - - 00000 SSR06 [R/W,R] 00001000 FSR06 [R] - - - 00000 SSR07 [R/W,R] 00001000 FSR07 [R] - - - 00000 Reserved BGR103 [R/W] 00000000 BGR105 [R/W] 00000000 BGR107 [R/W] 00000000
000064H
LIN-USART 4 with FIFO
000068H
00006CH
LIN-USART 5 with FIFO
000070H
000074H
LIN-USART 6 with FIFO
000078H
00007CH
LIN-USART 7 with FIFO
000080H 000084H 000088H 00008CH 000090H to 0000CCH
Reserved
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MB91460H Series
Address +0 0000D0H 0000D4H 0000D8H 0000DCH 0000E0H 0000E4H 0000E8H to 0000FCH 000100H 000104H 000108H 000110H 000114H 000118H 00011CH 000120H 000124H 000128H 00012CH 000130H 000134H GCN10 [R/W] 00110010 00010000 GCN11 [R/W] 00110010 00010000 GCN12 [R/W] 00110010 00010000 PTMR00 [R] 11111111 11111111 PDUT00 [W] XXXXXXXX XXXXXXXX PTMR01 [R] 11111111 11111111 PDUT01 [W] XXXXXXXX XXXXXXXX PTMR02 [R] 11111111 11111111 PDUT02 [W] XXXXXXXX XXXXXXXX PTMR03 [R] 11111111 11111111 PDUT03 [W] XXXXXXXX XXXXXXXX PTMR04 [R] 11111111 11111111 PDUT04 [W] XXXXXXXX XXXXXXXX IBCR0 [R/W] 00000000 ITMKH0 [R/W] 00 - - - - 11 Reserved IBCR1 [R/W] 00000000 ITMKH1 [R/W] 00 - - - - 11 Reserved +1 IBSR0 [R] 00000000 ITMKL0 [R/W] 11111111 IDAR0 [R/W] 00000000 IBSR1 [R] 00000000 ITMKL1 [R/W] 11111111 IDAR1 [R/W] 00000000 Register +2 ITBAH0 [R/W] - - - - - - 00 ISMK0 [R/W] 01111111 ICCR0 [R/W] - 0011111 ITBAH1 [R/W] - - - - - - 00 ISMK1 [R/W] 01111111 ICCR1 [R/W] - 0011111 +3 ITBAL0 [R/W] 00000000 ISBA0 [R/W] - 0000000 Reserved ITBAL1 [R/W] 00000000 ISBA1 [R/W] - 0000000 Reserved I2C 1 I2C 0 Block
Reserved GCN20 [R/W] - - - - 0000 GCN21 [R/W] - - - - 0000 GCN22 [R/W] - - - - 0000
Reserved PPG Control 0 to 3 PPG Control 4 to 7 PPG Control 8 to 11
Reserved Reserved Reserved
PCSR00 [W] XXXXXXXX XXXXXXXX PCNH00 [R/W] 0000000 PCNL00 [R/W] 000000 - 0
PPG 0
PCSR01 [W] XXXXXXXX XXXXXXXX PCNH01 [R/W] 0000000 PCNL01 [R/W] 000000 - 0
PPG 1
PCSR02 [W] XXXXXXXX XXXXXXXX PCNH02 [R/W] 0000000 PCNL02 [R/W] 000000 - 0
PPG 2
PCSR03 [W] XXXXXXXX XXXXXXXX PCNH03 [R/W] 0000000 PCNL03 [R/W] 000000 - 0
PPG 3
PCSR04 [W] XXXXXXXX XXXXXXXX PCNH04 [R/W] 0000000 PCNL04 [R/W] 000000 - 0
PPG 4
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Address +0 000138H 00013CH 000140H 000144H 000148H 00014CH 000150H 000154H 000158H 00015CH 000160H 000164H 000168H 00016CH 000170H to 00017CH 000180H 000184H 000188H Reserved +1 PTMR05 [R] 11111111 11111111 PDUT05 [W] XXXXXXXX XXXXXXXX PTMR06 [R] 11111111 11111111 PDUT06 [W] XXXXXXXX XXXXXXXX PTMR07 [R] 11111111 11111111 PDUT07 [W] XXXXXXXX XXXXXXXX PTMR08 [R] 11111111 11111111 PDUT08 [W] XXXXXXXX XXXXXXXX PTMR09 [R] 11111111 11111111 PDUT09 [W] XXXXXXXX XXXXXXXX PTMR10 [R] 11111111 11111111 PDUT10 [W] XXXXXXXX XXXXXXXX PTMR11 [R] 11111111 11111111 PDUT11 [W] XXXXXXXX XXXXXXXX Register +2 +3 PCSR05 [W] XXXXXXXX XXXXXXXX PCNH05 [R/W] 0000000 PCNL05 [R/W] 000000 - 0 Block
PPG 5
PCSR06 [W] XXXXXXXX XXXXXXXX PCNH06 [R/W] 0000000 PCNL06 [R/W] 000000 - 0
PPG 6
PCSR07 [W] XXXXXXXX XXXXXXXX PCNH07 [R/W] 0000000 PCNL07 [R/W] 000000 - 0
PPG 7
PCSR08 [W] XXXXXXXX XXXXXXXX PCNH08 [R/W] 0000000 PCNL08 [R/W] 000000 - 0
PPG 8
PCSR09 [W] XXXXXXXX XXXXXXXX PCNH09 [R/W] 0000000 PCNL09 [R/W] 000000 - 0
PPG 9
PCSR10 [W] XXXXXXXX XXXXXXXX PCNH10 [R/W] 0000000 PCNL10 [R/W] 000000 - 0
PPG 10
PCSR11 [W] XXXXXXXX XXXXXXXX PCNH11 [R/W] 0000000 Reserved PCNL11 [R/W] 000000 - 0
PPG 11
Reserved ICS23 [R/W] 00000000 Input Capture 0 to 3
ICS01 [R/W] 00000000
Reserved
IPCP0 [R] XXXXXXXX XXXXXXXX IPCP2 [R] XXXXXXXX XXXXXXXX
IPCP1 [R] XXXXXXXX XXXXXXXX IPCP3 [R] XXXXXXXX XXXXXXXX
DS07-16616-1E
49
MB91460H Series
Address +0 00018CH 000190H 000194H 000198H 00019CH 0001A0H 0001A4 0001A8H 0001ACH 0001B0H +1 OCS01 [R/W] - - - 0 - - 00 0000 - - 00 OCCP0 [R/W] XXXXXXXX XXXXXXXX OCCP2 [R/W] XXXXXXXX XXXXXXXX SGCRH [R/W] 0000 - - 00 SGAR [R/W] 00000000 SGCRL [R/W] - - 0 - - 000 Reserved Register +2 +3 OCS23 [R/W] - - - 0 - - 00 0000 - - 00 OCCP1 [R/W] XXXXXXXX XXXXXXXX OCCP3 [R/W] XXXXXXXX XXXXXXXX SGFR [R/W, R] XXXXXXXX XXXXXXXX SGTR [R/W] XXXXXXXX SGDR [R/W] XXXXXXXX Sound Generator Output Compare 0 to 3 Block
ADERH [R/W] 00000000 00000000 ADCS1 [R/W] 00000000 ADCT1 [R/W] 00010000 Reserved ADCS0 [R/W] 00000000 ADCT0 [R/W] 00101100 ACSR0 [R/W] -11XXX00
ADERL [R/W] 00000000 00000000 ADCR1 [R] 000000XX ADSCH [R/W] - - - 00000 Reserved ADCR0 [R] XXXXXXXX ADECH [R/W] - - - 00000 Reserved Alarm Comparator 0 to 1 A/D Converter
TMRLR0 [W] XXXXXXXX XXXXXXXX Reserved TMRLR1 [W] XXXXXXXX XXXXXXXX Reserved TMRLR2 [W] XXXXXXXX XXXXXXXX Reserved TMRLR3 [W] XXXXXXXX XXXXXXXX Reserved TMRLR4 [W] XXXXXXXX XXXXXXXX Reserved
TMR0 [R] XXXXXXXX XXXXXXXX TMCSRH0 [R/W] - - - 00000 TMCSRL0 [R/W] 0 - 000000
0001B4H
Reload Timer 0 (PPG 0, PPG 1)
0001B8H
TMR1 [R] XXXXXXXX XXXXXXXX TMCSRH1 [R/W] - - - 00000 TMCSRL1 [R/W] 0 - 000000
0001BCH
Reload Timer 1 (PPG 2, PPG 3)
0001C0H
TMR2 [R] XXXXXXXX XXXXXXXX TMCSRH2 [R/W] - - - 00000 TMCSRL2 [R/W] 0 - 000000
0001C4H
Reload Timer 2 (PPG 4, PPG 5)
0001C8H
TMR3 [R] XXXXXXXX XXXXXXXX TMCSRH3 [R/W] - - - 00000 TMCSRL3 [R/W] 0 - 000000
0001CCH
Reload Timer 3 (PPG 6, PPG 7)
0001D0H
TMR4 [R] XXXXXXXX XXXXXXXX TMCSRH4 [R/W] - - - 00000 TMCSRL4 [R/W] 0 - 000000
0001D4H
Reload Timer 4 (PPG 8, PPG 9)
50
DS07-16616-1E
MB91460H Series
Address +0 0001D8H +1 TMRLR5 [W] XXXXXXXX XXXXXXXX Reserved TMRLR6 [W] XXXXXXXX XXXXXXXX Reserved TMRLR7 [W] XXXXXXXX XXXXXXXX Reserved Register +2 +3 TMR5 [R] XXXXXXXX XXXXXXXX TMCSRH5 [R/W] - - - 00000 TMCSRL5 [R/W] 0 - 000000 Block
0001DCH
Reload Timer 5 (PPG 10, PPG 11)
0001E0H
TMR6 [R] XXXXXXXX XXXXXXXX TMCSRH6 [R/W] - - - 00000 TMCSRL6 [R/W] 0 - 000000
0001E4H
Reload Timer 6 (PPG 12, PPG 13)
0001E8H
TMR7 [R] XXXXXXXX XXXXXXXX TMCSRH7 [R/W] - - - 00000 Reserved TMCSRL7 [R/W] 0 - 000000 TCCS0 [R/W] 00000000 TCCS1 [R/W] 00000000 TCCS2 [R/W] 00000000 TCCS3 [R/W] 00000000
0001ECH
Reload Timer 7 (PPG 14, PPG 15) (A/D Converter) Free Running Timer 0 (ICU 0, ICU 1) Free Running Timer 1 (ICU 2, ICU 3) Free Running Timer 2 (OCU 0, OCU 1) Free Running Timer 3 (OCU 2, OCU 3)
0001F0H
TCDT0 [R/W] XXXXXXXX XXXXXXXX TCDT1 [R/W] XXXXXXXX XXXXXXXX TCDT2 [R/W] XXXXXXXX XXXXXXXX TCDT3 [R/W] XXXXXXXX XXXXXXXX
0001F4H
Reserved
0001F8H
Reserved
0001FCH
Reserved
000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH
DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB0 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB1 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB2 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB3 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 51
DMAC
DS07-16616-1E
MB91460H Series
Address +0 000220H 000224H 000228H to 00023CH 000240H 000244H to 0002CCH 0002D0H 0002D4H 0002D8H 0002DCH 0002E0H 0002E4H 0002E8H to 0002ECH 0002F0H TCDT4 [R/W] XXXXXXXX XXXXXXXX TCDT5 [R/W] XXXXXXXX XXXXXXXX TCDT6 [R/W] XXXXXXXX XXXXXXXX TCDT7 [R/W] XXXXXXXX XXXXXXXX Reserved DMACR [R/W] 00 - - 0000 Reserved ICS045 [R/W] 00000000 ICS67 [R/W] 00000000 Input Capture 4 to 7 +1 Register +2 +3 DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMAC Reserved Block
Reserved
Reserved
Reserved
IPCP4 [R] XXXXXXXX XXXXXXXX IPCP6 [R] XXXXXXXX XXXXXXXX OCS45 [R/W] - - - 0 - - 00 0000 - - 00 OCCP4 [R/W] XXXXXXXX XXXXXXXX OCCP6 [R/W] XXXXXXXX XXXXXXXX Reserved
IPCP5 [R] XXXXXXXX XXXXXXXX IPCP7 [R] XXXXXXXX XXXXXXXX OCS67 [R/W] - - - 0 - - 00 0000 - - 00 OCCP5 [R/W] XXXXXXXX XXXXXXXX OCCP7 [R/W] XXXXXXXX XXXXXXXX
Output Compare 4 to 7
Reserved Free Running Timer 4 (ICU 4, ICU 5) Free Running Timer 5 (ICU 6, ICU 7) Free Running Timer 6 (OCU 4, OCU 5) Free Running Timer 7 (OCU 6, OCU 7)
Reserved
TCCS4 [R/W] 00000000 TCCS5 [R/W] 00000000 TCCS6 [R/W] 00000000 TCCS7 [R/W] 00000000
0002F4H
Reserved
0002F8H
Reserved
0002FCH
Reserved
52
DS07-16616-1E
MB91460H Series
Address +0 000300H 000304H 000308H 00030CH to 00031CH 000320H 000324H to 00032CH 000330H 000334H 000338H 00033CH 000340H 000344H 000348H 00034CH 000350H to 00038CH 000390H 000394H to 0003ECH ROMS [R] 11111111 01000011 Reserved PTMR12 [R] 11111111 11111111 PDUT12 [W] XXXXXXXX XXXXXXXX PTMR13 [R] 11111111 11111111 PDUT13 [W] XXXXXXXX XXXXXXXX PTMR14 [R] 11111111 11111111 PDUT14 [W] XXXXXXXX XXXXXXXX PTMR15 [R] 11111111 11111111 PDUT15 [W] XXXXXXXX XXXXXXXX GCN13 [R/W] 00110010 00010000 Reserved PCSR12 [W] XXXXXXXX XXXXXXXX PCNH12 [R/W] 0000000 PCNL12 [R/W] 000000 - 0 UDRC1 [W] 00000000 UDCCH0 [R/W] 00000000 UDCCH1 [R/W] 00000000 +1 UDRC0 [W] 00000000 UDCCL0 [R/W] 00001000 UDCCL1 [R/W] 00001000 Reserved GCN23 [R/W] - - - - 0000 Register +2 UDCR1 [R] 00000000 Reserved Reserved +3 UDCR0 [R] 00000000 UDCS0 [R/W] 00000000 UDCS1 [R/W] 00000000 Reserved PPG Control 12 to 15 Reserved Up/Down Counter 0 to 1 Block
Reserved
PPG 12
PCSR13 [W] XXXXXXXX XXXXXXXX PCNH13 [R/W] 0000000 PCNL13 [R/W] 000000 - 0
PPG 13
PCSR14 [W] XXXXXXXX XXXXXXXX PCNH14 [R/W] 0000000 PCNL14 [R/W] 000000 - 0
PPG 14
PCSR15 [W] XXXXXXXX XXXXXXXX PCNH15 [R/W] 0000000 Reserved PCNL15 [R/W] 000000 - 0
PPG 15
Reserved
Reserved
ROM Select Register
Reserved
DS07-16616-1E
53
MB91460H Series
Address +0 0003F0H 0003F4H 0003F8H 0003FCH 000400H to 00043CH 000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H 00046CH 000470H 000474H 000478H ICR00 [R/W] ---11111 ICR04 [R/W] ---11111 ICR08 [R/W] ---11111 ICR12 [R/W] ---11111 ICR16 [R/W] ---11111 ICR20 [R/W] ---11111 ICR24 [R/W] ---11111 ICR28 [R/W] ---11111 ICR32 [R/W] ---11111 ICR36 [R/W] ---11111 ICR40 [R/W] ---11111 ICR44 [R/W] ---11111 ICR48 [R/W] ---11111 ICR52 [R/W] ---11111 ICR56 [R/W] ---11111 +1 Register +2 +3 BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved ICR01 [R/W] ---11111 ICR05 [R/W] ---11111 ICR09 [R/W] ---11111 ICR13 [R/W] ---11111 ICR17 [R/W] ---11111 ICR21 [R/W] ---11111 ICR25 [R/W] ---11111 ICR29 [R/W] ---11111 ICR33 [R/W] ---11111 ICR37 [R/W] ---11111 ICR41 [R/W] ---11111 ICR45 [R/W] ---11111 ICR49 [R/W] ---11111 ICR53 [R/W] ---11111 ICR57 [R/W] ---11111 ICR02 [R/W] ---11111 ICR06 [R/W] ---11111 ICR10 [R/W] ---11111 ICR14 [R/W] ---11111 ICR18 [R/W] ---11111 ICR22 [R/W] ---11111 ICR26 [R/W] ---11111 ICR30 [R/W] ---11111 ICR34[R/W] ---11111 ICR38 [R/W] ---11111 ICR42 [R/W] ---11111 ICR46 [R/W] ---11111 ICR50 [R/W] ---11111 ICR54 [R/W] ---11111 ICR58 [R/W] ---11111 ICR03 [R/W] ---11111 ICR07 [R/W] ---11111 ICR11 [R/W] ---11111 ICR15 [R/W] ---11111 ICR19 [R/W] ---11111 ICR23 [R/W] ---11111 ICR27 [R/W] ---11111 ICR31 [R/W] ---11111 ICR35 [R/W] ---11111 ICR39 [R/W] ---11111 ICR43 [R/W] ---11111 ICR47 [R/W] ---11111 ICR51 [R/W] ---11111 ICR55 [R/W] ---11111 ICR59 [R/W] ---11111 Interrupt Controller Block
Bit Search Module
54
DS07-16616-1E
MB91460H Series
Address +0 00047CH 000480H 000484H 000488H 00048CH 000490H PLLDIVM [R/W] - - - - 0000 PLLCTRL [R/W] - - - - 0000 OSCC1 [R/W] - - - - - 010 PORTEN [R/W] - - - - - - 00 Reserved Reserved WTHR [R/W] - - - 00000 CSVTR [R/W] - - - 00010 WTCER [R/W] - - - - - - 00 OSCS1 [R/W] 00001111 ICR60 [R/W] ---11111 RSRR [R/W] 10000000 CLKR [R/W] - - - - 0000 +1 ICR61 [R/W] ---11111 STCR [R/W] 00110011 WPR [W] XXXXXXXX PLLDIVN [R/W] - - 000000 Register +2 ICR62 [R/W] ---11111 TBCR [R/W] 00XXXX00 DIVR0 [R/W] 00000011 PLLDIVG [R/W] - - - - 0000 Reserved OSCC2 [R/W] - - - - - 010 Reserved WTCR [R/W] 00000000 000 - 00 - 0 Real Time Clock (Watch Timer) OSCS2 [R/W] 00001111 Main/Sub Oscillator Control (Reserved) Port Input Enable Control +3 ICR63 [R/W] ---11111 CTBR [W] XXXXXXXX DIVR1 [R/W] 00000000 PLLMULG [R/W] 00000000 Interrupt Controller Block
Clock Control Reserved
Reserved
PLL Interface
000494H
000498H 0004A0H 0004A4H 0004A8H
WTBR [R/W] - - - XXXXX XXXXXXXX XXXXXXXX WTMR [R/W] - - 000000 CSVCR [R/W] - 011100 WTSR [R/W] - - 000000 CSCFG [R/W] 0X000000 Reserved CMCFG [R/W] 00000000
0004ACH
ClockSupervisor /Selector/ Monitor Calibration of Sub Clock
0004B0H 0004B4H 0004B8H 0004BCH 0004C0H
CUCR [R/W] - - - - - - - - - - - 0 - - 00 CUTR1 [R] - - - - - - - - 00000000 CMPR [R/W] - - 000010 11111101 CMT1 [R/W] 00000000 1 - - - 0000 CANPRE [R/W] 0 - - - 0000 LVSEL [R/W] 00000111 OSCRH [R/W] 000 - - 001 CANCKD [R/W] - - 000000 LVDET [R/W] 00000 - 00 OSCRL [R/W] - - - - - 000
CUTD [R/W] 10000000 00000000 CUTR2 [R] 00000000 00000000 Reserved CMCR [R/W] - 001 - - 00
CMT2 [R/W] - - 000000 - - 000000 Reserved HWWDE [R/W] - - - - - - 00 WPCRH [R/W] 000 - - 001 HWWD [R/W,W] 00011000 WPCRL [R/W] - - - - - - 00
Clock Modulator
CAN Clock Control Low Voltage Detection/ Hardware Watchdog Main-/Sub-Oscillation Stabilisation Timer
0004C4H
0004C8H
DS07-16616-1E
55
MB91460H Series
Address +0 OSCCR [R/W] - - - - - - 00 +1 Register +2 REGSEL [R/W] - - 000110 +3 REGCTR [R/W] - - - 0 - - 00 Main- Oscillation Standby Control / Main/Sub Regulator Control Reserved ACR0 [R/W] 1111**00 00000000*2 ACR1 [R/W] XXXXXXXX XXXXXXXX ACR2 [R/W] XXXXXXXX XXXXXXXX ACR3 [R/W] XXXXXXXX XXXXXXXX ACR4 [R/W] XXXXXXXX XXXXXXXX ACR5 [R/W] XXXXXXXX XXXXXXXX ACR6 [R/W] XXXXXXXX XXXXXXXX ACR7 [R/W] XXXXXXXX XXXXXXXX AWR1 [R/W] XXXXXXXX XXXXXXXX AWR3 [R/W] XXXXXXXX XXXXXXXX AWR5 [R/W] XXXXXXXX XXXXXXXX AWR7 [R/W] XXXXXXXX XXXXXXXX Reserved External Bus Unit Block
0004CCH
Reserved
0004D0H to 00063CH 000640H 000644H 000648H 00064CH 000650H 000654H 000658H 00065CH 000660H 000664H 000668H 00066CH 000670H 000674H 000678H 00067CH 000680H 000684H CSER [R/W] 00000001 RCRH [R/W] 00XXXXXX IOWR0 [R/W] XXXXXXXX ASR0 [R/W] 00000000 00000000 ASR1 [R/W] XXXXXXXX XXXXXXXX ASR2 [R/W] XXXXXXXX XXXXXXXX ASR3 [R/W] XXXXXXXX XXXXXXXX ASR4 [R/W] XXXXXXXX XXXXXXXX ASR5 [R/W] XXXXXXXX XXXXXXXX ASR6 [R/W] XXXXXXXX XXXXXXXX ASR7 [R/W] XXXXXXXX XXXXXXXX AWR0 [R/W] 01111111 11111*11 AWR2 [R/W] XXXXXXXX XXXXXXXX AWR4 [R/W] XXXXXXXX XXXXXXXX AWR6 [R/W] XXXXXXXX XXXXXXXX MCRA [R/W] XXXXXXXX
Reserved
MCRB [R/W] XXXXXXXX Reserved IOWR1 [R/W] XXXXXXXX CHER [R/W] 11111111 RCRL [R/W] XXXX0XXX
IOWR2 [R/W] XXXXXXXX
IOWR3 [R/W] XXXXXXXX TCR [R/W] 0000**** *3
Reserved Reserved
Reserved
56
DS07-16616-1E
MB91460H Series
Address +0 000688H to 0007F8H 0007FCH 000800H to 000CFCH 000D00H 000D04H 000D08H 000D0CH 000D10H 000D14H 000D18H 000D1CH 000D20H to 000D3CH 000D40H 000D44H 000D48H 000D4CH 000D50H 000D54H 000D58H 000D5CH DDR00 [R/W] 00000000 Reserved DDR08 [R/W] 0 - - 0 - - -0 PDRD00 [R] XXXXXXXX Reserved PDRD08 [R] X - - X - - -X Reserved +1 Reserved MODR [W] XXXXXXXX Reserved PDRD01 [R] XXXXXXXX PDRD05 [R] - - XXXXXX PDRD09 [R] - - - - - - XX Register +2 +3 External Bus Unit Block
Reserved
Mode Register
Reserved
Reserved PDRD06 [R] XXXXXXXX PDRD10 [R] -------X PDRD14 [R] XXXXXXXX PDRD18 [R] - XXX - XXX PDRD22 [R] XXXXXXXX PDRD26 [R] XXXXXXXX PDRD07 [R] XXXXXXXX Reserved PDRD15 [R] XXXXXXXX PDRD19 [R] - XXX - XXX PDRD23 [R] XXXXXXXX PDRD27 [R] XXXXXXXX R-bus Port Data Direct Read Register
Reserved PDRD16 [R] XXXXXXXX PDRD20 [R] - XXX - XXX PDRD24 [R] XXXXXXXX PDRD28 [R] XXXXXXXX PDRD17 [R] XXXXXXXX PDRD21 [R] -------X Reserved PDRD29 [R] XXXXXXXX
Reserved
Reserved DDR01 [R/W] 00000000 DDR05 [R/W] - - 000000 DDR09 [R/W] - - - - - - 00
Reserved DDR06 [R/W] 00000000 DDR10 [R/W] - - - - - - -0 DDR14 [R/W] 00000000 DDR18 [R/W] - 000 - 000 DDR22 [R/W] 00000000 DDR26 [R/W] 00000000 DDR07 [R/W] 00000000 Reserved DDR15 [R/W] 00000000 DDR19 [R/W] - 000 - 000 DDR23 [R/W] 00000000 DDR27 [R/W] 00000000 R-bus Port Direction Register
Reserved DDR16 [R/W] 00000000 DDR20 [R/W] - 000 - 000 DDR24 [R/W] 00000000 DDR28 [R/W] 00000000 DDR17 [R/W] 00000000 DDR21 [R/W] - - - - - - 00 Reserved DDR29 [R/W] 00000000
Reserved 57
DS07-16616-1E
MB91460H Series
Address +0 000D60H to 000D7CH 000D80H 000D84H 000D88H 000D8CH 000D90H 000D94H 000D98H 000D9CH 000DA0H to 000DC4H 000DC8H 000DCCH 000DD0H 000DD4H 000DD8H 000DDCH to 000DFCH Reserved Reserved EPFR16 [R/W] 0 - 00 - - - EPFR20 [R/W] - 000 - 000 Reserved EPFR21 [R/W] ---- ---PFR00 [R/W] 11111111 Reserved PFR08 [R/W] 1 - - 1 - - 11 +1 Reserved PFR01 [R/W] 11111111 PFR05 [R/W] - - 111111 PFR09 [R/W] - - - - - - 11 Register +2 +3 Reserved Block
Reserved PFR06 [R/W] 11111111 PFR10 [R/W] - - - - - - -1 PFR14 [R/W] 00000000 PFR18 [R/W] - 000 - 000 PFR22 [R/W] 0000-0-0 PFR26 [R/W] 00000000 PFR07 [R/W] 11111111 Reserved PFR15 [R/W] 00000000 PFR19 [R/W] - 000 - 000 PFR23 [R/W] -0000000 PFR27 [R/W] 00000000 R-bus Port Function Register
Reserved PFR16 [R/W] 00000000 PFR20 [R/W] - 000 - 000 PFR24 [R/W] 00000000 PFR28 [R/W] 00000000 PFR17 [R/W] 00000000 PFR21 [R/W] - - - - - - 00 Reserved PFR29 [R/W] 00000000
Reserved
Reserved EPFR10 [R/W] -------0 EPFR14 [R/W] 00000000 EPFR18 [R/W] - 000 - 000
Reserved EPFR15 [R/W] 00000000 EPFR19 [R/W] - 0- - - 0- R-bus Port Extra Function Register
Reserved EPFR26 [R/W] 00000000 EPFR27 [R/W] 00000000 Reserved
Reserved
Reserved
58
DS07-16616-1E
MB91460H Series
Address +0 000E00H 000E04H 000E08H 000E0CH 000E10H 000E14H 000E18H 000E1CH 000E20H to 000E3CH 000E40H 000E44H 000E48H 000E4CH 000E50H 000E54H 000E58H 000E5CH 000E60H to 000E7CH PILR00 [R/W] 00000000 Reserved PILR08 [R/W] 0--0---0 PODR00 [R/W] 00000000 Reserved PODR08 [R/W] 0--0---0 +1 PODR01 [R/W] 00000000 PODR05 [R/W] - - 000000 PODR09 [R/W] - - - - - - 00 Register +2 Reserved PODR06 [R/W] 00000000 PODR10 [R/W] -------0 PODR14 [R/W] 00000000 PODR18 [R/W] - 000 - 000 PODR22 [R/W] 00000000 PODR26 [R/W] 00000000 PODR07 [R/W] 00000000 Reserved PODR15 [R/W] 00000000 PODR19 [R/W] - 000 - 000 PODR23 [R/W] 00000000 PODR27 [R/W] 00000000 R-bus Port Output Drive Select Register +3 Block
Reserved PODR16 [R/W] 00000000 PODR20 [R/W] - 000 - 000 PODR24 [R/W] 00000000 PODR28 [R/W] 00000000 PODR17 [R/W] 00000000 PODR21 [R/W] - - - - - - 00 Reserved PODR29 [R/W] 00000000
Reserved
Reserved PILR01 [R/W] 00000000 PILR05 [R/W] - - 000000 PILR09 [R/W] - - - - - - 00
Reserved
Reserved PILR06 [R/W] 00000000 PILR10 [R/W] -------0 PILR14 [R/W] 00000000 PILR18 [R/W] - - - - - 000 PILR22 [R/W] 00000000 PILR26 [R/W] 00000000 PILR07 [R/W] 00000000 Reserved PILR15 [R/W] 00000000 PILR19 [R/W] - 000 - 000 PILR23 [R/W] 00000000 PILR27 [R/W] 00000000 R-bus Port Input Level Select Register
Reserved PILR16 [R/W] 00000000 PILR20 [R/W] - 000 - 000 PILR24 [R/W] 00000000 PILR28 [R/W] 00000000 PILR17 [R/W] 00000000 PILR21 [R/W] - - - - - - 00 Reserved PILR29 [R/W] 00000000
Reserved
Reserved
Reserved
DS07-16616-1E
59
MB91460H Series
Address +0 000E80H 000E84H 000E88H 000E8CH 000E90H 000E94H 000E98H 000E9CH 000EA0H to 000EBCH 000EC0H 000EC4H 000EC8H 000ECCH 000ED0H 000ED4H 000ED8H 000EDCH 000EE0H to 000EFCH PPER00 [R/W] 00000000 Reserved PPER08 [R/W] 0--0---0 EPILR00 [R/W] 00000000 Reserved EPILR08 [R/W] 0 - - 0- - - 0 +1 EPILR01 [R/W] 00000000 EPILR05 [R/W] - - 000000 EPILR09 [R/W] - - - - - - 00 Register +2 Reserved EPILR06 [R/W] 00000000 EPILR10 [R/W] -------0 EPILR14 [R/W] 00000000 EPILR18 [R/W] - - - - - 000 EPILR22 [R/W] 00000000 EPILR26 [R/W] 00000000 EPILR07 [R/W] 00000000 Reserved EPILR15 [R/W] 00000000 EPILR19 [R/W] - 000 - 000 EPILR23 [R/W] 00000000 EPILR27 [R/W] 00000000 R-bus Port Extra Input Level Select Register +3 Block
Reserved EPILR16 [R/W] 00000000 EPILR20 [R/W] - 000 - 000 EPILR24 [R/W] 00000000 EPILR28 [R/W] 00000000 EPILR17 [R/W] 00000000 EPILR21 [R/W] - - - - - - 00 Reserved EPILR29 [R/W] 00000000
Reserved
Reserved PPER01 [R/W] 00000000 PPER05 [R/W] - - 000000 PPER09 [R/W] - - - - - - 00
Reserved
Reserved PPER06 [R/W] 00000000 PPER10 [R/W] -------0 PPER14 [R/W] 00000000 PPER18 [R/W] - 000 - 000 PPER22 [R/W] 00000000 PPER26 [R/W] 00000000 PPER07 [R/W] 00000000 Reserved PPER15 [R/W] 00000000 PPER19 [R/W] - 000 - 000 PPER23 [R/W] 00000000 PPER27 [R/W] 00000000 R-bus Port Pull-Up/Down Enable Register
Reserved PPER16 [R/W] 00000000 PPER20 [R/W] - 000 - 000 PPER24 [R/W] 00000000 PPER28 [R/W] 00000000 PPER17 [R/W] 00000000 PPER21 [R/W] - - - - - - 00 Reserved PPER29 [R/W] 00000000
Reserved
Reserved
Reserved
60
DS07-16616-1E
MB91460H Series
Address +0 000F00H 000F04H 000F08H 000F0CH 000F10H 000F14H 000F18H 000F1CH 000F20H to 000F3CH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H 001024H 001028H to 003FFCH PPCR00 [R/W] 11111111 Reserved PPCR08 [R/W] 1--1---1 +1 PPCR01 [R/W] 11111111 PPCR05 [R/W] - - 111111 PPCR09 [R/W] - - - - - - 11 Register +2 Reserved PPCR06 [R/W] 11111111 PPCR10 [R/W] -------1 PPCR14 [R/W] 00000000 PPCR18 [R/W] - 111- 111 PPCR22 [R/W] 11111111 PPCR26 [R/W] 11111111 PPCR07 [R/W] 11111111 Reserved PPCR15 [R/W] 11111111 PPCR19 [R/W] - 111- 111 PPCR23 [R/W] 11111111 PPCR27 [R/W] 11111111 R-bus Port Pull-Up/Down Control Register +3 Block
Reserved PPCR16 [R/W] 00000000 PPCR20 [R/W] - 111- 111 PPCR24 [R/W] 11111111 PPCR28 [R/W] 11111111 PPCR17 [R/W] 00000000 PPCR21 [R/W] - - - - - - 11 Reserved PPCR29 [R/W] 11111111
Reserved
Reserved DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved
Reserved
DMAC
Reserved
DS07-16616-1E
61
MB91460H Series
Address +0 002000H to 006FFCH 007000H 007004H 007008H 00700CH 007010H 007014H to 007FFCH 008000H to 00BFFCH 00C000H 00C004H 00C008H 00C00CH +1 Register +2 +3 Flash-cache / I-RAM area Block
Flash-cache size is 8 Kbytes : 004000H to 005FFCH FMCS [R/W] 01101000 FMCR [R/W] - - - - 0000 FCHCR [R/W] - - - - - - 00 10000011 Reserved FMPS [R/W] - - - - - 000
FMWT [R/W] 11111111 11111111
FMAC [R] 00000000 00000000 00000000 00000000 FCHA0 [R/W] - - - - - - - - - - 000000 00000000 00000000 FCHA1 [R/W] - - - - - - - - - - 000000 00000000 00000000 Reserved
Flash Memory/ I-Cache Control Register
I-Cache Non-cacheable area setting Register
Reserved
Boot-ROM size is 4 Kbytes : 00B000H to 00BFFCH (instruction access is 1 wait cycle, data access is 1 wait cycle) CTRLR0 [R/W] 00000000 00000001 ERRCNT0 [R] 00000000 00000000 INTR0 [R] 00000000 00000000 BRPE0 [R/W] 00000000 00000000 STATR0 [R/W] 00000000 00000000 BTR0 [R/W] 00100011 00000001 TESTR0 [R/W] 00000000 X0000000 CBSYNC0
Boot ROM area
CAN 0 Control Register
62
DS07-16616-1E
MB91460H Series
Address +0 00C010H 00C014H 00C018H 00C01CH 00C020H 00C024H 00C028H to 00C02CH 00C030H 00C034H 00C038H to 00C03CH 00C040H 00C044H 00C048H IF2CREQ0 [R/W] 00000000 00000001 IF2MSK20 [R/W] 11111111 11111111 IF2ARB20 [R/W] 00000000 00000000 IF1DTA20 [R/W] 00000000 00000000 IF1DTB20 [R/W] 00000000 00000000 Reserved IF2CMSK0 [R/W] 00000000 00000000 IF2MSK10 [R/W] 11111111 11111111 IF2ARB10 [R/W] 00000000 00000000 CAN 0 IF 2 Register +1 IF1CREQ0 [R/W] 00000000 00000001 IF1MSK20 [R/W] 11111111 11111111 IF1ARB20 [R/W] 00000000 00000000 IF1MCTR0 [R/W] 00000000 00000000 IF1DTA10 [R/W] 00000000 00000000 IF1DTB10 [R/W] 00000000 00000000 Reserved IF1DTA10 [R/W] 00000000 00000000 IF1DTB10 [R/W] 00000000 00000000 Register +2 +3 IF1CMSK0 [R/W] 00000000 00000000 IF1MSK10 [R/W] 11111111 11111111 IF1ARB10 [R/W] 00000000 00000000 Reserved IF1DTA20 [R/W] 00000000 00000000 IF1DTB20 [R/W] 00000000 00000000 CAN 0 IF 1 Register Block
DS07-16616-1E
63
MB91460H Series
Address +0 00C04CH 00C050H 00C054H 00C058H to 00C05CH 00C060H 00C064H 00C068H to 00C07CH 00C080H 00C084H to 00C08CH 00C090H 00C094H to 00C09CH 00C0A0H 00C0A4H to 00C0ACH 00C0B0H 00C0B4H to 00C0FCH 00C100H to 00EFFCH TREQR20 [R] 00000000 00000000 Reserved NEWDT20 [R] 00000000 00000000 Reserved INTPND20 [R] 00000000 00000000 Reserved MSGVAL20 [R] 00000000 00000000 Reserved IF2DTA20 [R/W] 00000000 00000000 IF2DTB20 [R/W] 00000000 00000000 Reserved TREQR10 [R] 00000000 00000000 Reserved NEWDT10 [R] 00000000 00000000 Reserved INTPND10 [R] 00000000 00000000 Reserved MSGVAL10 [R] 00000000 00000000 Reserved CAN 0 Status Flags +1 IF2MCTR0 [R/W] 00000000 00000000 IF2DTA10 [R/W] 00000000 00000000 IF2DTB10 [R/W] 00000000 00000000 Reserved IF2DTA10 [R/W] 00000000 00000000 IF2DTB10 [R/W] 00000000 00000000 Register +2 Reserved IF2DTA20 [R/W] 00000000 00000000 IF2DTB20 [R/W] 00000000 00000000 +3 Block
Reserved
Reserved
64
DS07-16616-1E
MB91460H Series
Address +0 00F000H 00F004H 00F008H 00F00CH 00F010H 00F014H to 00F01CH 00F020H 00F024H 00F028H 00F02CH 00F030H to 00F07CH +1
Register +2 +3 BCTRL [R/W] - - - - - - - - - - - - - - - - 11111100 00000000 BSTAT [R/W] - - - - - - - - - - - - - 000 00000000 10 - - 000000 BIAC [R] - - - - - - - - - - - - - - - - 00000000 00000000 BOAC [R] - - - - - - - - - - - - - - - - 00000000 00000000 BIRQ [R/W] - - - - - - - - - - - - - - - - 00000000 00000000
Block
EDSU / MPU Reserved BCR0 [R/W] - - - - - - - - 00000000 00000000 00000000 BCR1 [R/W] - - - - - - - - 00000000 00000000 00000000 BCR2 [R/W] - - - - - - - - 00000000 00000000 00000000 BCR3 [R/W] - - - - - - - - 00000000 00000000 00000000 Reserved Reserved
DS07-16616-1E
65
MB91460H Series
Address +0 00F080H 00F084H 00F088H 00F08CH 00F090H 00F094H 00F098H 00F09CH 00F0A0H 00F0A4H 00F0A8H 00F0ACH 00F0B0H 00F0B4H 00F0B8H 00F0BCH 00F0C0H to 01FFFCH 020000H to 02FFFCH 030000H to 03FFFCH +1 Register +2 +3 BAD0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD5 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD6 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD7 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD8 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD9 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD10 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD11 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD12 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD13 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD14 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD15 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved EDSU / MPU Block
EDSU / MPU
D-RAM size is 16 Kbytes : 02C000H - 02FFFCH (data access is 0 wait cycles) ID-RAM size is 16 Kbytes : 030000H - 033FFCH (instruction access is 0 wait cycles, data access is 1 wait cycle)
D-RAM area
ID-RAM area
*1 : depends on the number of available CAN channels 66 DS07-16616-1E
MB91460H Series
*2 : ACR0 [11 : 10] depends on Mode vector fetch information on bus width *3 : TCR [3 : 0] INIT value = 0000, keeps value after RST
DS07-16616-1E
67
MB91460H Series
2. Flash memory and external bus area 2.1. MB91F464HB
32bit read 16bit read/write Address 040000H to 05FFF8H 060000H to 07FFF8H 080000H to 09FFF8H 0A0000H to 0BFFF8H 0C0000H to 0DFFF8H 0E0000H to 0FFFF0H 0FFFF8H 100000H to 11FFF8H 120000H to 13FFF8H 140000H to 143FF8H 144000H to 17FF8H 148000H to 14BFF8H 14C000H to 14FFF8H 150000H to17FFF8H SA4 (8KB) SA6 (8KB) Reserved (Continued) dat[31:0] dat[31:16] +0 +1 dat[15:0] +2 +3 Register +4 +5 +6 +7 Reserved Reserved Reserved SA14 (64KB) SA16 (64KB) SA18 (64KB) FMV [R] 06 00 00 00H External Bus Area External Bus Area SA5 (8KB) SA7 (8KB) ROMS7 Reserved Reserved Reserved SA15 (64KB) SA17 (64KB) SA19 (64KB) FRV [R] 00 00 BF F8H ROMS5 dat[31:0] dat[31:16] dat[15:0] Block ROMS0 ROMS1 ROMS2 ROMS3 ROMS4
ROMS6
68
DS07-16616-1E
MB91460H Series
(Continued) 32bit read 16bit read/write Address 180000H to 1BFFF8H 1C0000H to 1FFFF8H 200000H to 27FFF8H 280000H to 2FFFF8H 300000H to 37FFF8H 380000H to 3FFFF8H 400000H to 47FFF8H 480000H to 4FFFF8H
dat[31:0] dat[31:16] +0 +1 dat[15:0] +2 +3 Register +4
dat[31:0] dat[31:16] +5 dat[15:0] +6 +7 Block
ROMS8
ROMS9
ROMS10
ROMS11 External Bus Area ROMS12
ROMS13
ROMS14
ROMS15
Note: Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values shown above will be read.
DS07-16616-1E
69
MB91460H Series
INTERRUPT VECTOR TABLE
Interrupt number Interrupt Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Hexadecimal 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Interrupt level *1 Setting Register -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FH fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 440H 441H 442H 443H 444H 445H 446H 447H Register address -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Interrupt vector *2 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H Default vector address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H
DMA Resource number
Reset Mode vector System reserved System reserved System reserved CPU supervisor mode (INT #5 instruction) *5 Memory Protection exception *5 System reserved System reserved System reserved System reserved System reserved System reserved System reserved Undefined instruction exception NMI request External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 External Interrupt 8 External Interrupt 9 External Interrupt 10 External Interrupt 11 External Interrupt 12 External Interrupt 13 External Interrupt 14 External Interrupt 15 70
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0, 16 1, 17 2, 18 3, 19 20 21 22 23 -- -- -- -- -- -- -- --
DS07-16616-1E
MB91460H Series
Interrupt number Interrupt Decimal 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
*4
Interrupt level *1 Setting Register ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 *3 ICR24 Register address 448H 449H 44AH 44BH 44CH 44DH 44EH 44FH 450H 451H 452H 453H 454H 455H 456H 457H 458H
Interrupt vector *2 Offset 37CH 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H Default vector address 000FFF7CH 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H
Hexadecimal 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41
DMA Resource number
Reload Timer 0 Reload Timer 1 Reload Timer 2 Reload Timer 3 Reload Timer 4 Reload Timer 5 Reload Timer 6 Reload Timer 7 Free Run Timer 0 Free Run Timer 1 Free Run Timer 2 Free Run Timer 3 Free Run Timer 4 Free Run Timer 5 Free Run Timer 6 Free Run Timer 7 CAN 0 Reserved Reserved Reserved Reserved Reserved LIN-USART 0 RX LIN-USART 0 TX Reserved Reserved LIN-USART 2 RX LIN-USART 2 TX LIN-USART 3 RX LIN-USART 3 TX System Reserved Delayed Interrupt System Reserved System Reserved *4 DS07-16616-1E
4, 32 5, 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 -- -- -- -- -- -- 6, 48 7, 49 8, 50 9, 51 52 53 54 55 -- -- -- -- 71
64 65
MB91460H Series
Interrupt number Interrupt Decimal 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Hexadecimal 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 Interrupt level *1 Setting Register ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 Register address 459H 45AH 45BH 45CH 45DH 45EH 45FH 460H 461H 462H 463H 464H 465H 466H 467H 468H 469H Interrupt vector *2 Offset 2F4H 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH 2B8H 2B4H 2B0H 2ACH 2A8H 2A4H 2A0H 29CH 298H 294H 290H 28CH 288H 284H 280H 27CH 278H 274H 270H Default vector address 000FFEF4H 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH 000FFEB8H 000FFEB4H 000FFEB0H 000FFEACH 000FFEA8H 000FFEA4H 000FFEA0H 000FFE9CH 000FFE98H 000FFE94H 000FFE90H 000FFE8CH 000FFE88H 000FFE84H 000FFE80H 000FFE7CH 000FFE78H 000FFE74H 000FFE70H
DMA Resource number
LIN-USART (FIFO) 4 RX LIN-USART (FIFO) 4 TX LIN-USART (FIFO) 5 RX LIN-USART (FIFO) 5 TX LIN-USART (FIFO) 6 RX LIN-USART (FIFO) 6 TX LIN-USART (FIFO) 7 RX LIN-USART (FIFO) 7 TX IC0 I2C 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Input Capture 0 Input Capture 1 Input Capture 2 Input Capture 3 Input Capture 4 Input Capture 5 Input Capture 6 Input Capture 7 72
2
10, 56 11, 57 12, 58 13, 59 60 61 62 63 -- -- 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87
DS07-16616-1E
MB91460H Series
Interrupt number Interrupt Decimal 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 Hexadecimal 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 Interrupt level *1 Setting Register ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 *3 ICR48 ICR49 ICR50 ICR51 ICR52 ICR53 ICR54 ICR55 ICR56 ICR57 ICR58 Register address 46AH 46BH 46CH 46DH 46EH 46FH 470H 471H 472H 473H 474H 475H 476H 477H 478H 479H 47AH Interrupt vector *2 Offset 26CH 268H 264H 260H 25CH 258H 254H 250H 24CH 248H 244H 240H 23CH 238H 234H 230H 22CH 228H 224H 220H 21CH 218H 214H 210H 20CH 208H 204H 200H 1FCH 1F8H 1F4H 1F0H 1ECH 1E8H Default vector address 000FFE6CH 000FFE68H 000FFE64H 000FFE60H 000FFE5CH 000FFE58H 000FFE54H 000FFE50H 000FFE4CH 000FFE48H 000FFE44H 000FFE40H 000FFE3CH 000FFE38H 000FFE34H 000FFE30H 000FFE2CH 000FFE28H 000FFE24H 000FFE20H 000FFE1CH 000FFE18H 000FFE14H 000FFE10H 000FFE0CH 000FFE08H 000FFE04H 000FFE00H 000FFDFCH 000FFDF8H 000FFDF4H 000FFDF0H 000FFDECH 000FFDE8H
DMA Resource number
Output Compare 0 Output Compare 1 Output Compare 2 Output Compare 3 Output Compare 4 Output Compare 5 Output Compare 6 Output Compare 7 Sound Generator Reserved System Reserved System Reserved PPG 0 PPG 1 PPG 2 PPG 3 PPG 4 PPG 5 PPG 6 PPG 7 PPG 8 PPG 9 PPG 10 PPG 11 PPG 12 PPG 13 PPG 14 PPG 15 Up/Down Counter 0 Up/Down Counter 1 Reserved Reserved Real Time Clock Calibration Unit DS07-16616-1E
88 89 90 91 92 93 94 95 -- -- -- -- 15, 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 -- -- -- -- -- -- 73
MB91460H Series
Interrupt number Interrupt Decimal 134 135 136 137 138 139 140 141 142 143 144 145 to 255 Hexadecimal 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 to FF Interrupt level *1 Setting Register ICR59 ICR60 ICR61 ICR62 ICR63 -- -- Register address 47BH 47CH 47DH 47EH 47FH -- -- Interrupt vector *2 Offset 1E4H 1E0H 1DCH 1D8H 1D4H 1D0H 1CCH 1C8H 1C4H 1C0H 1BCH 1B8H to 000H Default vector address 000FFDE4H 000FFDE0H 000FFDDCH 000FFDD8H 000FFDD4H 000FFDD0H 000FFDCCH 000FFDC8H 000FFDC4H 000FFDC0H 000FFDBCH 000FFDB8H to 000FFC00H
DMA Resource number
A/D Converter 0 System reserved Alarm Comparator 0 Reserved Low Voltage Detection Reserved Time base Overflow PLL Clock Gear DMA Controller Main/Sub OSC stability wait Security vector Used by the INT instruction.
14, 112 -- -- -- -- -- -- -- -- -- -- --
*1 : The Interrupt Control Registers (ICRs) are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is provided for each interrupt request. *2 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (TBR) . The TBR specifies the top of the EIT vector table. The addresses listed in the table are for the default TBR value (000FFC00H) . The TBR is initialized to this value by a reset. The TBR is set to 000FFC00H after the internal boot ROM is executed. *3 : ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03H : IOS[0]) *4 : Used by REALOS *5 : Memory Protection Unit (MPU) support
74
DS07-16616-1E
MB91460H Series
RECOMMENDED SETTINGS
1. PLL and Clockgear settings
Please note that for MB91F464HB the core base clock frequencies are valid in the 1.8V operation mode of the Main regulator and Flash . Recommended PLL divider and clockgear settings PLL Input (CLK) [MHz] 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Frequency Parameter DIVM 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 4 4 6 8 10 12 DIVN 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 Clockgear Parameter DIVG 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 MULG 24 24 24 24 20 20 20 20 16 16 16 16 12 12 12 24 24 24 24 24 28 32 32 200 192 184 176 168 160 152 144 136 128 120 112 104 96 88 160 144 128 112 144 160 160 144 PLL Output (X) [MHz] Core Base Clock [MHz] 100 96 92 88 84 80 76 72 68 64 60 56 52 48 44 40 36 32 28 24 20 16 12
Remarks
MULG
DS07-16616-1E
75
MB91460H Series
2. Clock Modulator settings
The following table shows all possible settings for the Clock Modulator in a base clock frequency range from 32MHz up to 88MHz. The Flash access time settings need to be adjusted according to Fmax while the PLL and clockgear settings should be set according to base clock frequency. Clock Modulator settings, frequency range and supported supply voltage Modulation Degree (k) 1 1 1 1 2 1 1 1 2 3 1 1 1 2 3 1 1 1 1 2 2 3 4 1 1 1 1 1 2 2 Random No (N) 3 3 3 5 3 3 5 7 3 3 3 5 7 3 3 3 5 7 9 3 5 3 3 3 5 7 9 11 3 5 CMPR [hex] 026F 026F 026F 02AE 046E 026F 02AE 02ED 046E 066D 026F 02AE 02ED 046E 066D 026F 02AE 02ED 032C 046E 04AC 066D 086C 026F 02AE 02ED 032C 036B 046E 04AC Baseclk [MHz] 88 84 80 80 80 76 76 76 76 76 72 72 72 72 72 68 68 68 68 68 68 68 68 64 64 64 64 64 64 64 Fmin [MHz] 79.5 76.1 72.6 68.7 68.7 69.1 65.3 62 65.3 62 65.5 62 58.8 62 58.8 62 58.7 55.7 53 58.7 53 55.7 53 58.5 55.3 52.5 49.9 47.6 55.3 49.9 Fmax [MHz] 98.5 93.8 89.1 95.8 95.8 84.5 90.8 98.1 90.8 98.1 79.9 85.8 92.7 85.8 92.7 75.3 80.9 87.3 95 80.9 95 87.3 95 70.7 75.9 82 89.1 97.6 75.9 89.1
76
DS07-16616-1E
MB91460H Series
Modulation Degree (k) 3 4 5 1 1 1 1 1 2 2 3 4 5 1 1 1 1 1 1 2 2 2 3 3 4 5 6 1 1 1 1 1 1 1 2 2 DS07-16616-1E Random No (N) 3 3 3 3 5 7 9 11 3 5 3 3 3 3 5 7 9 11 13 3 5 7 3 5 3 3 3 3 5 7 9 11 13 15 3 5 CMPR [hex] 066D 086C 0A6B 026F 02AE 02ED 032C 036B 046E 04AC 066D 086C 0A6B 026F 02AE 02ED 032C 036B 03AA 046E 04AC 04EA 066D 06AA 086C 0A6B 0C6A 026F 02AE 02ED 032C 036B 03AA 03E9 046E 04AC Baseclk [MHz] 64 64 64 60 60 60 60 60 60 60 60 60 60 56 56 56 56 56 56 56 56 56 56 56 56 56 56 52 52 52 52 52 52 52 52 52 Fmin [MHz] 52.5 49.9 47.6 54.9 51.9 49.3 46.9 44.7 51.9 46.9 49.3 46.9 44.7 51.4 48.6 46.1 43.8 41.8 39.9 48.6 43.8 39.9 46.1 39.9 43.8 41.8 39.9 47.8 45.2 42.9 40.8 38.8 37.1 35.5 45.2 40.8 Fmax [MHz] 82 89.1 97.6 66.1 71 76.7 83.3 91.3 71 83.3 76.7 83.3 91.3 61.6 66.1 71.4 77.6 84.9 93.8 66.1 77.6 93.8 71.4 93.8 77.6 84.9 93.8 57 61.2 66.1 71.8 78.6 86.8 96.9 61.2 71.8 77
MB91460H Series
Modulation Degree (k) 2 3 3 4 5 6 7 1 1 1 1 1 1 1 2 2 2 3 3 4 5 6 7 1 1 1 1 1 1 1 2 2 2 2 3 3 78 Random No (N) 7 3 5 3 3 3 3 3 5 7 9 11 13 15 3 5 7 3 5 3 3 3 3 3 5 7 9 11 13 15 3 5 7 9 3 5 CMPR [hex] 04EA 066D 06AA 086C 0A6B 0C6A 0E69 026F 02AE 02ED 032C 036B 03AA 03E9 046E 04AC 04EA 066D 06AA 086C 0A6B 0C6A 0E69 026F 02AE 02ED 032C 036B 03AA 03E9 046E 04AC 04EA 0528 066D 06AA Baseclk [MHz] 52 52 52 52 52 52 52 48 48 48 48 48 48 48 48 48 48 48 48 48 48 48 48 44 44 44 44 44 44 44 44 44 44 44 44 44 Fmin [MHz] 37.1 42.9 37.1 40.8 38.8 37.1 35.5 44.2 41.8 39.6 37.7 35.9 34.3 32.8 41.8 37.7 34.3 39.6 34.3 37.7 35.9 34.3 32.8 40.6 38.4 36.4 34.6 33 31.5 30.1 38.4 34.6 31.5 28.9 36.4 31.5 Fmax [MHz] 86.8 66.1 86.8 71.8 78.6 86.8 96.9 52.5 56.4 60.9 66.1 72.3 79.9 89.1 56.4 66.1 79.9 60.9 79.9 66.1 72.3 79.9 89.1 48.1 51.6 55.7 60.4 66.1 73 81.4 51.6 60.4 73 92.1 55.7 73 DS07-16616-1E
MB91460H Series
ELECTRICAL CHARACTERISTICS
1. Absolute maximum ratings
Parameter Power supply slew rate Power supply voltage 1*
1 1
Symbol VDD5R VDD5
Rating Min - 0.3 - 0.3 VDD5-0.3 VDD35-0.3 Max 50 + 6.0 + 6.0 VDD5+0.3 VDD35+0.3
Unit V/ms V V
Remarks
Power supply voltage 2*
V
Relationship of the supply voltages
AVCC5 VSS5-0.3 VDD35-0.3 VDD5+0.3 VDD35+0.3 + 6.0 + 6.0 VDD5 + 0.3 AVcc5 + 0.3 VDD5 + 0.3 + 4.0 20 10 8 100 50 - 10 -4 - 100 - 25 600 + 105 + 150 V V V V V V mA mA mA mA mA mA mA mA mA mA mW C C
At least one pin of the Ports 26 to 29 (ANn) is used as digital input or output. All pins of the Ports 26 to 29 (ANn) follow the condition of VIA *2 *2
Analog power supply voltage*1 Analog reference power supply voltage*1 Input voltage 1*1 Analog pin input voltage*1 Output voltage 1*1 Maximum clamp current Total maximum clamp current "L" level maximum output current*4 "L" level average output current*5 "L" level total maximum output current "L" level total average output current*6 "H" level maximum output current*4 "H" level average output current*5 "H" level total maximum output current "H" level total average output current*6 Power consumption Operating temperature Storage temperature
AVCC5 AVRH VI1 VIA VO1 ICLAMP |ICLAMP| IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg
- 0.3 - 0.3 Vss5 - 0.3 AVss5 - 0.3 Vss5 - 0.3 - 4.0 - 40 - 55
*3 *3
at TA = 105C
*1 : The parameter is based on VSS5 = AVSS5 = 0.0 V. DS07-16616-1E 81
MB91460H Series
2. Recommended operating conditions
(VSS5 = AVSS5 = 0.0 V) Parameter Symbol VDD5 Power supply voltage VDD5R AVCC5 Smoothing capacitor at VCC18C pin Power supply slew rate Operating temperature Main Oscillation stabilisation time Lock-up time PLL (4 MHz ->16 ...100MHz) ESD Protection (Human body model) RC Oscillator Vsurge fRC100kHz fRC2MHz 2 50 1 100 2 200 4 TA CS Value Min 3.0 3.0 3.0 - 40 10 0.6 Typ 4.7 Max 5.5 5.5 5.5 50 + 105 Unit V V V F V/ms C ms ms kV Rdischarge = 1.5k Cdischarge = 100pF Internal regulator A/D converter Use a X7R ceramic capacitor or a capacitor that has similar frequency characteristics. Remarks
kHz VDDCORE > 1.65V MHz
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.
VCC18C
VSS5 CS
AVSS5
DS07-16616-1E
83
MB91460H Series
3. DC characteristics
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 C to + 105 C) Parameter Symbol Pin name Condition Port inputs if CMOS Hysteresis 0.8/0.2 input is selected Value Min 0.8 x VDD Typ Max VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 Unit Remarks CMOS hysteresis input 4.5 V < VDD < 5.5 V 3 V < VDD < 4.5 V
V V V V
VIH VIHR INITX MD_3 to MD_0 X0, X0A
Port inputs if CMOS 0.7 x VDD Hysteresis 0.7/0.3 0.74 x VDD input is selected AUTOMOTIVE Hysteresis input is selected Port inputs if TTL input is selected Port inputs if CMOS Hysteresis 0.8/0.2 input is selected Port inputs if CMOS Hysteresis 0.7/0.3 input is selected Port inputs if AUTOMOTIVE Hysteresis input is selected Port inputs if TTL input is selected 0.8 x VDD
Input "H" voltage
2.0
VDD + 0.3
V INITX input pin (CMOS Hysteresis) Mode input pins External clock in "Oscillation mode" External clock in "Fast Clock Input mode"
0.8 x VDD
VDD + 0.3
V
VIHM VIHX0S
VDD - 0.3 2.5
VDD + 0.3 VDD + 0.3
V V
VIHX0F
X0
0.8 x VDD
VDD + 0.3
V
VSS - 0.3
0.2 x VDD
V
VIL Input "L" voltage VILR INITX MD_3 to MD_0 X0, X0A
VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3

0.3 x VDD 0.5 x VDD 0.46 x VDD 0.8
V V V V INITX input pin (CMOS Hysteresis) Mode input pins External clock in "Oscillation mode" 4.5 V < VDD < 5.5 V 3 V < VDD < 4.5 V
VSS - 0.3
0.2 x VDD
V
VILM VILXDS
VSS - 0.3 VSS - 0.3
VSS + 0.3 0.5
V V
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Pin name Value Min Typ Max
Parameter Symbol
Condition
Unit
Remarks
Input capacitance
CIN
All except VDD5, VDD5R, f = 1 MHz VSS5, AVCC5, AVSS5, AVRH5 CLKB: 100 MHz CLKP: 50 MHz VDD5R CLKT: 50 MHz CLKCAN: 50 MHz TA = + 25 C TA = + 105 C TA = + 25 C TA = + 105 C TA = + 25 C TA = + 105 C
-
5
15
pF
ICC
-
100
130
mA A A A A A A A A A A
Code fetch from Flash
-
30 300 100 500 50 400 70 50 250 20
150 2000 500 2400 250 2200 150 100 500 40
At stop mode *5 RTC : 4 MHz mode *5 RTC : 100 kHz mode *5 External low voltage detection Internal low voltage detection Main clock (4 MHz) Sub clock (32 kHz)
Power supply current MB91 F464HB
ICCH
VDD5R
ILVE ILVI
VDD5 VDD5R
-
IOSC
VDD5 -
1. 2. 3. 4.
Pnn_m includes all GPIO pins. Analog (AN) channels and PullUp/PullDown are disabled. ANn includes all pins where AN channels are enabled. Pnn_m includes all GPIO pins. The pull up resistors must be enabled by PPER/PPCR setting and the pins must be in input direction. Pnn_m includes all GPIO pins. The pull down resistors must be enabled by PPER/PPCR setting and the pins must be in input direction.
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4. A/D converter characteristics
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 C to + 105 C) Parameter Resolution Total error Nonlinearity error Differential nonlinearity error Zero reading voltage Full scale reading voltage Symbol Pin name VOT VFST ANn ANn Value Min -3 - 2.5 - 1.9 AVRL- 1.5 LSB AVRH- 3.5 LSB 0.6 Compare time Tcomp 2.0 s s Typ AVRL + 0.5 LSB AVRH- 1.5 LSB Max 10 +3 + 2.5 + 1.9 AVRL + 2.5 LSB AVRH + 0.5 LSB 16,500 Unit bit LSB LSB LSB V V s 4.5 V AVCC5 5.5 V 3.0 V AVCC5 4.5 V 4.5 V AVCC5 5.5 V, REXT < 2 k 3.0 V AVCC5 4.5 V, REXT < 1 k 4.5 V AVCC5 5.5 V 3.0 V AVCC5 4.5 V 4.5 V AVCC5 5.5 V 3.0 V AVCC5 4.5 V TA = + 25 C TA = + 105 C Remarks
0.4 Sampling time Tsamp 1.0

11 2.6 12.1 +1 +3 AVRH 4
s s s pF k k A A V LSB
1.0 Conversion time Tconv 3.0 Input capacitance CIN ANn Input resistance RIN ANn Analog input leakage current Analog input voltage range Offset between input channels IAIN VAIN ANn ANn ANn -1 -3 AVRL
(Continued) Note : The accuracy gets worse as AVRH - AVRL becomes smaller
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Definition of A/D converter terms * Resolution Analog variation that is recognizable by the A/D converter. * Nonlinearity error Deviation between actual conversion characteristics and a straight line connecting the zero transition point (00 0000 0000B 00 0000 0001B) and the full scale transition point (11 1111 1110B 11 1111 1111B). * Differential nonlinearity error Deviation of the input voltage from the ideal value that is required to change the output code by 1 LSB. * Total error This error indicates the difference between actual and theoretical values, including the zero transition error, full scale transition error, and nonlinearity error.
Total error
3F
H
3FE
H
1.5LSB'
3FD
H
Actual conversion characteristics
(N-1)+0.5LSB'} {1LSB'
Digital output
04
H
VNT
03
H
(measurement value)
H
02 01
H
Actual conversion characteristics
Ideal characteristics
0.5LSB' VA
S
5
VRH A
Analog input
1LSB' (ideal value) = AVRH - AVSS5 [V] 1024 Total error of digital output N = VNT - {1 LSB' x (N - 1) + 0.5 LSB'} 1 LSB' N : A/D converter digital output value VOT' (ideal value) = AVSS5 + 0.5 LSB' [V] VFST' (ideal value) = AVRH - 1.5 LSB' [V] VNT : Voltage at which the digital output changes from (N + 1) H to NH (Continued)
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MB91460H Series
(Continued)
Nonlinearity error
3F
H
Differential nonlinearity error
Actual conversion characteristics
Actual conversion characteristics
H
3FE 3FD
(N+1)
H
{1LSB(N-1)+V
H
TO
}
VFST
(measurement value)
Digital output
Digital output
Ideal characteristics
N
H
04
H
VNT
03
H
(measurement value)
(N-1)
H
VFST VNT
(measurement value)
02
H
Actual conversion characteristics
(measurement value)
Ideal characteristics
01
H
(N-2)
H
VTO (measurement value)
VA
S
Actual conversion characteristics
S
5
VRH A
VA
5
VRH A
Analog input
Analog input
Nonlinearity error of digital output N =
VNT - {1LSB x (N - 1) + VOT} [LSB] 1LSB V (N + 1) T - VNT 1LSB - 1 [LSB]
Differential nonlinearity error of digital output N = 1LSB = VFST - VOT 1022 [V]
N : A/D converter digital output value VOT : Voltage at which the digital output changes from 000H to 001H. VFST : Voltage at which the digital output changes from 3FEH to 3FFH.
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5. Alarm comparator characteristics
Parameter Symbol Pin name Value Min Typ Max Unit Remarks Alarm comparator enabled in fast mode (per channel) *1 Alarm comparator enabled in normal mode (per channel)
*1
IA5ALMF
25
40
A
Power supply current
AVCC5 IA5ALMS 7 10 A
IA5ALMH ALARM pin input current ALARM pin input voltage range Alarm upper limit voltage Alarm lower limit voltage Alarm hysteresis voltage Alarm input resistance IALIN
-1 -3 0

5 +1 +3 AVCC5
A A A V
Alarm comparator disabled TA=25 C TA=105 C
VALIN
VIAH
AVCC5 x 0.78 - 3% AVCC5 x 0.36 - 5% ALARM_n
AVCC5 x 0.78
AVCC5 x 0.78 + 3% AVCC5 x 0.36 + 5%
V
VIAL
AVCC5 x 0.36
V
VIAHYS
50
0.1
250 0.2
mV
RIN
5
M s Alarm comparator enabled in fast mode *1 Alarm comparator enabled in normal mode
*1
tCOMPF Comparion time tCOMPS
1
2
s
Note: *1 :
The fast Alarm Comparator mode is enabled by setting ACSR.MD=1 Setting ACSR.MD=0 sets the normal mode.
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MB91460H Series
6. FLASH memory program/erase characteristics 6.1. MB91F464HB
Value Min 10 000 20 Typ 0.9 n*0.9 23 Max 3.6 n*3.6 370
(TA = 25oC, Vcc = 5.0V)
Parameter Sector erase time Chip erase time Word (16-bit or 32-bit width) programming time Programme/Erase cycle Flash data retention time Unit s s s cycle year *1 Remarks Erasure programming time not included n is the number of Flash sector of the device System overhead time not included
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85oC)
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7. AC characteristics 7.1. Clock timing
(VDD5 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter Symbol Pin name X0 X1 X0A X1A Value Min 3.5 32 Typ 4 32.768 Max 16 100 Unit MHz kHz Condition Opposite phase external supply or crystal
Clock frequency
fC
* Clock timing condition
tC
X0, X1, X0A, X1A
PWH PWL
0.8 VCC 0.2 VCC
7.2.
Reset input ratings
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 C to + 105 C) Parameter Symbol Pin name Condition Value Min 8 tINTL INITX 20 s Max Unit ms
INITX input time (at power-on) INITX input time (other than the above)
tINTL
INITX
0.2 VCC
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* Internal clock mode (master mode)
tSCYCI
SCKn for ESCR:SCES = 0
VOL
VOH
VOL
SCKn for ESCR:SCES = 1
VOH VOL
VOH
tSLOVI
tOVSHI VOH VOL tIVSHI VIH VIL
SOTn
tSHIXI VIH VIL
SINn
* External clock mode (slave mode)
tSLSHE tSHSLE VOH VOL VOL VOL
SCKn for ESCR:SCES = 0
VOH
SCKn for ESCR:SCES = 1
VOL tFE
VOH
VOH tRE
VOL
VOH
tSLOVE VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL
SOTn
SINn
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MB91460H Series
7.4. I2C AC Timings at VDD5 = 3.0 to 5.5 V
* Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 3 mA - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = - 40 C to + 105 C - Cl = 50 pF - VOL = 0.3 x VDD5 - VOH = 0.7 x VDD5 - EPILR = 0, PILR = 0 (CMOS Hysteresis 0.3 x VDD5/0.7 x VDD5) Fast mode: (VDD5 = 3.5 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 C to + 105 C) Parameter SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition Data hold time for I2C-bus devices Data setup time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Setup time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Pulse width of spike suppressed by input filter Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb tSP Pin name SCLn SCLn, SDAn SCLn SCLn SCLn, SDAn SCLn, SDAn SCLn SDAn SCLn, SDAn SCLn, SDAn SCLn, SDAn SCLn, SDAn SCLn, SDAn SCLn, SDAn Value Min 0 0.6 1.3 0.6 0.6 0 100 20 + 0.1Cb 20 + 0.1Cb 0.6 1.3 0 Max 400 0.9 300 300 400 (1..1.5) x tCLKP Unit kHz s s s s s ns ns ns s s pF ns *1 Remark
*1 The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles of peripheral clock, depending on the phase relationship between I2C signals (SDA, SCL) and peripheral clock. Note: tCLKP is the cycle time of the peripheral clock.
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Sr
tr
S
P
S
tf
SDA
tBUF tHD;DAT tSU;DAT tHD;STA tSU;STA tSP tSU;ST0
tHD;STA
SCL
tLOW tHIGH
tf
tr
MB91460H Series
97
MB91460H Series
7.5. Free-run timer clock
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 C to + 105 C) Parameter Input pulse width Symbol tTIWH tTIWL Pin name CKn Condition Value Min 4tCLKP Max Unit ns
Note : tCLKP is the cycle time of the peripheral clock.
CKn
VIH
VIH VIL
tTIWH tTIWL
VIL
7.6.
Trigger input timing
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 C to + 105 C) Parameter Symbol tINP tATGX Pin name ICUn ATGX Condition Value Min 5tCLKP 5tCLKP Max Unit ns ns
Input capture input trigger A/D converter trigger
Note : tCLKP is the cycle time of the peripheral clock.
tATGX, tINP
ICUn, ATGX
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7.7. External Bus AC Timings at VDD35 = 3.0 to 5.5 V
* Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD35 = 4.5 V to 5.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = - 40 C to + 105 C - Cl = 50 pF - VOL = 0.5 x VDD35 - VOH = 0.5 x VDD35 - EPILR = 0, PILR = 1 (Automotive Level = worst case)
7.7.1.
Basic Timing
(VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter Symbol tCLCH tCHCL tCLCSL tCLCSH tCHCSL tCLAV SYSCLK A21 to A0 SYSCLK CSXn Pin name SYSCLK Value Min 1/2 x tCLKT - 1 1/2 x tCLKT - 9 -6 Max 1/2 x tCLKT + 9 1/2 x tCLKT + 1 8 12 +1 13 Unit ns ns ns ns ns ns
SYSCLK SYSCLK to CSXn delay time SYSCLK to CSXn delay time (Addr CS delay) SYSCLK to Address valid delay time
Note : tCLKT is the cycle time of the external bus clock.
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MB91460H Series
7.7.2. Synchronous/Asynchronous read access
(VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter SYSCLK to RDX delay time Data valid to RDX setup time RDX to Data valid hold time SYSCLK to WRXn (as byte enable) delay time SYSCLK to CSXn delay time Symbol TCHRL TCHRH TDSRH TRHDX TCLWRL TCLWRH TCLCSL TCLCSH Pin name SYSCLK RDX RDX D31 to D16 RDX D31 to D16 SYSCLK WRXn SYSCLK CSXn Value Min -7 -4 33 0 0 Max 1 2 8 8 12 Unit ns ns ns ns ns ns ns ns
SYSCLK
tCLCSL tCLCSH
CSXn
tCLWRL
tCLWRH
WRXn (as byte enable)
tCHRH tCHRL
RDX
tDSRH
tRHDX
DATA IN
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MB91460H Series
7.7.3. Synchronous write access
(VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter SYSCLK to WRXn delay time Data valid to WRXn setup time WRXn to Data valid hold time SYSCLK to CSXn delay time Symbol TCLWRL TCLWRH TDSWRL TWRHDH TCLCSL TCLCSH Pin name SYSCLK WRXn WRXn D31 to D16 WRXn D31 to D16 SYSCLK CSXn Value Min 0 -7 tCLKT - 20 Max 8 8 12 Unit ns ns ns ns ns ns
SYSCLK
tCLCSL
tCLCSH
CSXn
tCLWRH tCLWRL
WRXn
tDSWRL
tWRHDH
DATA OUT
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7.7.4. Asynchronous write access
(VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter WRXn to WRXn pulse width Data valid to WRXn setup time WRXn to Data valid hold time WRXn to CSXn delay time Symbol TWRLWRH TDSWRL TWRHDH TCLWRL TWRHCH Pin name WRXn WRXn D31 to D16 WRXn D31 to D16 WRXn CSXn Value Min tCLKT 1/2 x tCLKT - 10 1/2 x tCLKT - 19 1/2 x tCLKT Max 1/2 x tCLKT Unit ns ns ns ns ns
CSXn
TCLWRL TWRLWRH TWRHCH
WRXn
TDSWRL
TWRHDH
DATA OUT
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MB91460H Series
7.7.5. RDY waitcycle insertion
(VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 C to + 105 C) Parameter RDY setup time RDY hold time Symbol TRDYS TRDYH Pin name SYSCLK RDY SYSCLK RDY Value Min 34 0 Max Unit ns ns
SYSCLK
tRDYS
tRDYH
RDY
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ORDERING INFORMATION
Part number MB91F464HBPMC-GSE2 Package 144-pin plastic LQFP (FPT-144P-M08) Remarks Lead-free package
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MB91460H Series
PACKAGE DIMENSION
144-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight 0.50 mm 20.0 x 20.0 mm Gullwing Plastic mold 1.70 mm MAX 1.20g P-LFQFP144-20x20-0.50
(FPT-144P-M08)
Code (Reference)
144-pin plastic LQFP (FPT-144P-M08)
22.000.20(.866.008)SQ
* 20.000.10(.787.004)SQ
108 73
Note 1) *:Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
0.1450.055 (.006.002)
109
72
0.08(.003)
Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
INDEX
0~8
0.100.10 (.004.004) (Stand off)
144
37
"A" LEAD No.
1 36
0.50(.020)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.25(.010)
0.220.05 (.009.002)
0.08(.003)
M
(c)2003-2008 FUJITSU MICROELECTRONICS LIMITED F144019S-c-4-7 C
2003 FUJITSU LIMITED F144019S-c-4-6
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/
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REVISION HISTORY
Version 2.0 Date 2009-01-07 Initial version Remark
DS07-16616-1E
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MEMO
DS07-16616-1E
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MB91460H Series
MEMO
DS07-16616-1E
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MB91460H Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department

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